• Smart Media Journal
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• v.9 no.4
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• pp.109-117
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• 2020

Recently, with the advent of the 4th industrial revolution, digital twins are emerging as an important technology that connects and integrates physical systems and cyber systems. In this article, we analyzed the major requirements of digital twins required for the construction of digital twins of power equipments in the energy field, focusing on the industry 4.0-based Asset Administration Shell(AAS). However, since not so many studies have been conducted yet on a common platform or demonstration model for implementing digital twins both domestically and internationally, digital twin requirements are analyzed with the consideration of digital twinning of power equipment in the energy field. Also, we suggested necessary procedures and specific functions of AAS to establish a smart energy digital twin in the future by analyzing the core requirements necessary for the construction and designing the AAS design for specific power equipment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.480-481
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• 2009

In the paper we study for the ubiquitous networking based on power line communication technology with digital signal transmission. The necessity of research for using resources in the network effectively is being increase as network to use the PLC with smart grid networking. The data rate has compared with implemented modem 250Mbps in the pixel resolution and bandwidth, which has degraded with 80%. We also proposed for design of high-definition digital signal transceiver, which has used in the network between digital multimedia with PLC. Using resources in the network effectively can be also verified with this research.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.375-381
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• 1999

In this study, turbine speed control algorithm is studied for Buk-Jeju steam turbine power plant and also digital governor system is designed for speed control of steam turbine in power plant. By using duplex I/O module, triplex CPU module, 2 out of 3 voting algorithm and adding self diagnostic ability, the reliability of the designed digital governor system can be acquired satisfactorily. Designed and manufactured digital governor system is implemented in a pilot steam turbine plant of 0.3kw output power Installed in Korea Maritime University. After a series of experiment the reliability and availability is confirmed and also stable operation is achieved.

• Proceedings of the Korean Reliability Society Conference
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• 2002.06a
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• pp.387-401
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• 2002

The Digital Engineered Safety Feature Actuation System (DESFAS) of nuclear power plants actuates safety systems to mitigate severe accidents occurred in nuclear power plants. The reliability of the system should be evaluated in order to meet the reliability criteria of nuclear power plants. In this work, we have calculated and evaluated the lifetime of DESFAS by using Reliability Block Diagram (RBD) and failure rates of digital control components. Surveillance test is assumed in the evaluation. The result shows that the digital control component can be used in DESFAS system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.1
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• pp.19-26
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• 2011

In this paper, we designed Interpolation FIR(Finite Impulse Response) filter and 1-bit SDM(Sigma- Delta Modulator) for small digital audio speaker, which has low power consumption and high output characteristics. In order to achieve high linearity and low distortion performance of the systems, we adopt Type I Chevychev FIR filter which has equiripple characteristics in the pass band and proposed high efficient FIR filter structure. SDM is the most efficient modulation technique among the noise shaping techniques. In this paper, we implemented SDM using CIFB(Cascade of Intergrators, Feed-Back) which is generally used in DAC of small digital audio speakers. The proposed SDM structure can achieve high SNR, high-efficiency characteristics and low power consumption in mobile devices. Also considering manufacture of SoC(System on Chip), we performed simulation with Matlab and Verilog HDL to obtain optimal number of operational bits and verified a good experimental results.

• Journal of Power Electronics
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• v.13 no.4
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• pp.600-608
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• 2013

This paper analyzes the effect of the admittance component for the digitally controlled single-phase bridgeless power factor correction (PFC) converter. To do this, it is shown how the digital delay effects such as the digital pulse-width modulation (DPWM) and the computation delays restrict the bandwidth of the converter. After that, the admittance effect of the entire digital control system is analyzed when the bridgeless PFC converter which has the limited bandwidth is connected to the grid. From this, the waveform distortion of the input current is explained and the compensation method for the admittance component is suggested to improve the quality of the input current. Both the simulations and the experiments are performed to verify the analyses taken in this paper for the 1 kW bridgeless PFC converter prototype.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.5
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• pp.175-181
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• 2002

In this paper, fault tolerant digital governor is designed to realize ceaseless controlling and to improve the reliability of control system. Designed digital governor huts duplex I/O module and triplex CPU module and also 2 out of 3 voting algorithm and self diagnostic ability. The Processor module of the system(SIDG-3000) is developed based on 32 Bit industrial microprocessor, which guaranteed high quality of the module and SRAM for data also SRAM for command are separated. The process module also includes inter process communication function and power back up function (SRAM for back-up). System reliability is estimated by using the model of Markov process. It is shown that the reliability of triplex system in mission time can be dramatically improved compared with a single control system Designed digital governor system is applied after modelling of the steam turbine generator system of Buk-Cheju Thermal Power Plant. Simulation is carried out to prove the effectiveness of the designed digital governor system

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.442-446
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• 1998

With the advent of the high-speed microprocessor and DSP, the possibility of executing a control strategy in digital domain has become a reality. By the use of the DSP and microprocessor controller, many high power converters such as especially inverter and motor drive system may be enhanced resulting in the improved robustness to EMI, the ability to communicate the operating conditions and the ease of adjusting the control parameters. But, the digital controller using DSP or microprocessor is not applied in the high frequency switching power supplies, especially full bridge dc/dc converter. So, this paper presents the method and realization of designing a digital-to-phase shift PWM circuit for full digital controlled phase-shifted full bridge dc/dc converter with zero voltage switching. The operating principles, simulation and experimental results will be presented.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.247-251
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• 2001

Universal motors are mainly used for vacuum cleaner application. There are a lot of researches on SRM that applys home appliance throughout the world. The manufacturing cost of SRM drive makes it hard to expand its application to home appliance. This paper presents Single Phase SRM for the vacuum cleaner that has advantge in cost and performance over conventional universal motor. This paper proposes new power device driving scheme by using SRM switching characteristic. The driving scheme is very simple and inexpensive. Dwell Time Control method is used for the minimum switching loss of power device. The switching frequency of power device is less than 4.5kHz at 45,000rpm. By use of this scheme, power device based on very small switching losses can be used on SRM drive. Also, the biggest problem in single phase SRM is starting, this paper shows a new starting algorithm with two hall sensors, accelerating and running sensors, respectively. Finally, the proposed Single Phase SRM achieves higher efficiency and long life time compared to universal motor. Its life time is more than 1500 hours. Its life time is extended 4 times than that of conventional motor and its suction power is increased $20\%$ at the same volume of conventional universal motor.