• Nuclear Engineering and Technology
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• 제50권1호
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• pp.203-210
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• 2018

As the modernization of the nuclear instrumentation system progresses, research reactors have adopted digital wide-range neutron power measurement (DWRNPM) systems. These systems typically monitor the neutron flux across a range of over 10 decades. Because neutron detectors only measure the local neutron flux at their position, the local neutron flux must be converted to total reactor power through calibration, which involves mapping the local neutron flux level to a reference reactor power. Conventionally, the neutron power range is divided into smaller subranges because the neutron detector signal characteristics and the reference reactor power estimation methods are different for each subrange. Therefore, many factors should be considered when preparing the calibration procedure for DWRNPM channels. The main purpose of this work is to serve as a reference for performing the calibration of DWRNPM systems in research reactors. This work provides a comprehensive overview of the calibration of DWRNPM channels by describing the configuration of the DWRNPM system and by summarizing the theories of operation and the reference power estimation methods with their associated calibration procedure. The calibration procedure was actually performed during the commissioning of an open-pool type research reactor, and the results and experience are documented herein.

• 한국정보통신학회논문지
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• 제18권8호
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• pp.1847-1853
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• 2014

이동통신 시스템의 OFDMA 방식은 신호에 대한 PAPR(Peak to Average Power Ratio) 값의 증가를 가져왔다. 이동통신 시스템 전력 소모의 대부분을 차지하는 전력 증폭기에 대한 효율 개선은 매우 중요한 핵심 기술이다. 전력 증폭기의 선형 특성 개선을 위해 디지털전치왜곡 기술을 사용하였으며, 전력 증폭기의 효율 개선을 위해 비대칭 도허티(Asymmetric Doherty) 방식을 사용하였다. 본 논문에서는 기존 비대칭 도허티 구조와 다른 새로운 구조의 비대칭 도허티 구조를 제안하였다. 제안하는 새로운 구조의 비대칭 도허티 방식에서는 전력 증폭기 구동단을 주경로와 첨두경로로 분리하였으며, 위상 변환기를 이용하여 도허티 증폭기의 전력 결합 특성을 개선하였다. 또한 구동단 첨두 증폭기 gate bais에 대한 포락선 추적 기술을 적용하여 효율을 개선하였다.

• 시스템엔지니어링학술지
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• 제5권1호
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• pp.33-41
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• 2009

The analog or partly digital typed interface of main control room in nuclear power plant (NPP) is gradually being replaced to the totally digitalized interface suitable for the digital environment. SKN 3,4 Nuclear Power Plant is currently developed in such a way to employ advanced displays and controls such as computerized procedure system(CPS), large display panel(LDP), and Soft control. According to the developed design process, the main control room (MCR) of the SKN3,4 was aesthetically designed based on a design concept of the health and sustainability and technically evaluated with human factors guidelines, which somehow lack of the confidence on the evaluation for the rapidly changing digital environment. The suitable review guideline for the digitalized interface and the environment was developed such as the guideline for CPS with information displays on VDU. For the guideline development, tremendous guidelines and technical papers related to evaluation issues of digital environment has been collected, analyzed and transformed to electric database forms and then built on database management system, called Design Review Supporting System to retrieve the appropriate issues for the practical usage of evaluators-in-field.

• Journal of Power Electronics
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• 제12권4호
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• pp.623-631
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• 2012

In this paper, a digital controller design procedure is presented for single-phase voltage-doubler boost rectifiers (VDBR). The model derivation of the single-phase VDBR is performed in the s-domain. After that the simplified equivalent z-domain models are derived. These z-domain models are utilized to design the input current and the output dc-link voltage controllers. For the controller design in the z-domain, the traditional K-factor method is modified by considering the nature of the digital controller. The frequency pre-warping and anti-windup techniques are adapted for the controller design. By using the proposed method, the phase margin and the control bandwidth are accurately achieved as required by controller designers in a practical frequency range. The proposed method is applied to a 2.5 kVA single-phase VDBR for Uninterruptible Power Supply (UPS) applications. From the simulation and the experimental results, the effectiveness of the proposed design method has been verified.

• Nuclear Engineering and Technology
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• 제41권4호
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• pp.447-454
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• 2009

This paper is a technical review of the research and development results of the Korea Nuclear Instrumentation and Control System (KNICS) project and Nu-Tech 2012 program. In these projects man-machine interface system architecture, two digital platforms, and several control and protection systems were developed. One platform is a Programmable Logic Controller (PLC) for a digital safety system and another platform is a Distributed Control System (DCS) for a non-safety control system. With the safety-grade platform PLC, a reactor protection system, an engineered safety feature-component control system, and reactor core protection system were developed. A power control system was developed based on the DCS. A logic alarm cause tracking system was developed as a man-machine interface for APR1400. Also, Integrated Performance Validation Facility (IPVF) was developed for the evaluation of the function and performance of developed I&C systems. The safety-grade platform PLC and the digital safety system obtained approval for the topical report from the Korean regulatory body in February of 2009. A utility and vendor company will determine the suitability of the KNICS and Nu- Tech 2012 products to apply them to the planned nuclear power plants.

• Journal of Power Electronics
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• 제17권3호
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• pp.821-834
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• 2017

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

• 전기전자학회논문지
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• 제22권3호
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• 디지털산업정보학회논문지
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• 제9권1호
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• pp.53-58
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• 2013

In this paper, we proposed low power algorithm for battery residual capacity and a task. Algorithm the mobile devices power of the battery residual capacity for the task to perform power consumption to reduce the frequency alters. Task is different in power consumption according to kinds of in time accomplishment device to use. Adjustment of power consumption analyzes kinds of given tasks from having the minimum power consumption task to having the maximum power consumption task. Control frequency so that power consumption waste to be exposed to battery residual capacity can be happened according to the results analyzed. Experiment the frequency by adjusting power consumption a method to reduce using [7] and in the same environment power of the battery residual capacity consider the task to perform frequency were controlled. Efficiency was proved compare with the experiment results [7]. The experiments results show increment in the number of processing by 45.46% comparing with that [7] algorithm.

• ETRI Journal
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• 제35권5호
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• pp.819-826
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• 2013

A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulse-code modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-${\mu}m$ CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 ${\mu}W$ from a 1.2-V power supply.

• 한국전자통신학회논문지
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• 제11권9호
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• pp.855-860
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• 2016

본 연구는 디지털위성중계기용 전원공급기의 설계 및 구현에 대해 기술하였다. 위성버스의 PLDIU(: Payload Distribution and Interface Unit)와 전원공급기의 인터페이스를 제시하였고, 우주환경에 대한 WCA(: Worst Case Analysis)를 통하여 ESD(: Electro Static Discharge) 등의 발생에 대한 회로 오동작 가능성을 최소화 시켰다. 발사환경 시 발생하는 진동 및 우주 방사능에 의한 TID(: Total Ionizing Dose)에 대한 시뮬레이션을 통해 신뢰성 있는 전원공급기를 설계하였으며, 제작 후 우주환경시험을 통하여 기능 및 성능에 문제없음을 확인하였다.