• Korean Journal of Remote Sensing
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• v.10 no.2
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• pp.37-48
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• 1994

In spatial information processing, particularly in non-renewable resource exploration, the spatial data sets, including remote sensing, geophysical and geochemical data, have to be geocoded onto a reference map and integrated for the final analysis and interpretation. Application of a computer based GIS(Geographical Information System of Geological Information System) at some point of the spatial data integration/fusion processing is now a logical and essential step. It should, however, be pointed out that the basic concepts of the GIS based spatial data fusion were developed with insufficient mathematical understanding of spatial characteristics or quantitative modeling framwork of the data. Furthermore many remote sensing and geological data sets, available for many exploration projects, are spatially incomplete in coverage and interduce spatially uneven information distribution. In addition, spectral information of many spatial data sets is often imprecise due to digital rescaling. Direct applications of GIS systems to spatial data fusion can therefore result in seriously erroneous final results. To resolve this problem, some of the important mathematical information representation techniques are briefly reviewed and discussed in this paper with condideration of spatial and spectral characteristics of the common remote sensing and exploration data. They include the basic probabilistic approach, the evidential belief function approach (Dempster-Shafer method) and the fuzzy logic approach. Even though the basic concepts of these three approaches are different, proper application of the techniques and careful interpretation of the final results are expected to yield acceptable conclusions in cach case. Actual tests with real data (Moon, 1990a; An etal., 1991, 1992, 1993) have shown that implementation and application of the methods discussed in this paper consistently provide more accurate final results than most direct applications of GIS techniques.

• The Journal of the Acoustical Society of Korea
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• v.41 no.5
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• pp.507-517
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• 2022

The PhotoAcoustic Microscopy (PAM) has been proved to be a useful tool for biological and medical applications due to its high spatial and contrast resolution. PAM is based on transmission of laser pulses and reception of PA signals. Since the strength of PA signals is generally low, not only are high-performance optical and acoustic modules required, but high-performance electronics for imaging are also particularly needed for high-quality PAM imaging. Most PAM systems are implemented with a combination of several pieces of equipment commercially available to receive, amplify, enhance, and digitize PA signals. To this end, PAM systems are inevitably bulky and not optimal because general purpose equipment is used. This paper reports a PA signal receiving system recently developed to attain the capability of improved Signal to Noise Ratio (SNR) and Contrast to Noise Ratio (CNR) of PAM images; the main module of this system is a low noise, wideband signal receiver that consists of two low-noise amplifiers, two variable gain amplifiers, analog filters, an Analog to Digital Converter (ADC), and control logic. From phantom imaging experiments, it was found that the developed system can improve SNR by 6.7 dB and CNR by 3 dB, compared to a combination of several pieces of commercially available equipment.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.