• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.184-193
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• 2015

This paper proposes a cost-efficient and automatic method for large data acquisition from a test chip without expensive equipment to characterize random process variation in an integrated circuit. Our method requires only a test chip, a personal computer, a cheap digital-to-analog converter, a controller and multimeters, and thus large volume measurement can be performed on an office desk at low cost. To demonstrate the proposed method, we designed a test chip with a current model logic driver and an array of 128 current mirrors that mimic the random process variation of the driver's tail current mirror. Using our method, we characterized the random process variation of the driver's voltage due to the random process variation on the driver's tail current mirror from large volume measurement data. The statistical characteristics of the driver's output voltage calculated from the measured data are compared with Monte Carlo simulation. The difference between the measured and the simulated averages and standard deviations are less than 20% showing that we can easily characterize the random process variation at low cost by using our cost-efficient automatic large data acquisition method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2317-2325
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• 2016

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) with a reference driver. The proposed SAR ADC consists of a capacitive digital-to-analog converter (CDAC), a comparator, a SAR logic, and a reference driver which improves the immunity to the power supply noise. The reference driver generates the reference voltages of 0.45 V and 1.35 V for the SAR ADC with an input voltage range of ${\pm}0.9V$. The SAR ADC is implemented using a $0.18-{\mu}m$ CMOS technology with a 1.8-V supply. The proposed SAR ADC including the reference driver almost maintains an input voltage range to be ${\pm}0.9V$ although the variation of supply voltage is +/- 200 mV. It consumes 5.32 mW at a sampling rate of 10 MS/s. The measured ENOB, DNL, and INL of the ADC are 9.11 bit, +0.60/-0.74 LSB, and +0.69/-0.65 LSB, respectively.

• Journal of Digital Convergence
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• v.17 no.7
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• pp.131-138
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• 2019

The world's electricity production ratio is 40% for coal, 20% for natural gas, 16% for hydroelectric power, 15% for nuclear power and 6% for petroleum. Fossil fuels also cause serious problems in terms of price and supply because of the high concentration of resources on the earth. Solar energy is attracting attention as a next-generation eco-friendly energy that will replace fossil fuels with these problems. In this study, we test the charge-operation plan and the discharge operation plan for peak-cut operation by applying the maximum power demand reduction simulation. To do this, we selected the electricity usage from November to February, which has the largest amount of power usage, and applied charge / discharge logic. Simulation results show that the contract power decreases as the peak demand power after the ESS Peak-cut service is reduced to 50% of the peak-target power. As a result, the contract power reduction can reduce the basic power value of the customer and not only the economic superiority can be expected, but also contribute to the improvement of the electric quality and stabilization of the power supply system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.1-9
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• 2009

A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.

• Journal of Internet Computing and Services
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• v.12 no.5
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• pp.47-61
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• 2011

Recently, the importance of digital forensic has been magnified because of the dramatic increase of cyber crimes and the increasing complexity of the investigation of target systems such as PCs, servers, and database systems. Moreover, some systems have to be investigated with live forensic techniques. However, even though live forensic techniques have been improved, they are still vulnerable to anti-forensic activities when the target systems are remotely accessible by criminals or their accomplices. To solve this problem, we first suggest a layer-based model and the anti-forensic scenarios which can actually be applicable to each layer. Our suggested model, the Anti-Forensic Activites layer-based model, has 5 layers - the physical layer, network layer, OS layer, database application layer and data layer. Each layer has possible anti-forensic scenarios with detailed commands. Second, we propose a fuzzy expert system for effectively detecting anti-forensic activities. Some anti-forensic activities are hardly distinguished from normal activities. So, we use fuzzy logic for handling ambiguous data. We make rule sets with extracted commands and their arguments from pre-defined scenarios and the fuzzy expert system learns the rule sets. With this system, we can detect anti-forensic activities in real time when performing live forensic.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.67-74
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• 2004

Differently from an existing analog control, because the digital control includes microprocessor basically, the digital control is enable to monitor internal parameters of DC-DC converter and to control output voltage remotely by communicating with a Windows based PC. These things are impossible in an analog control and there are more advantages in a digital control than an analog control. In this paper, with the advantages mentioned above, the feasibility of digital controlled DC-DC converter in low price is proposed. In order to implement these functions, it is used the inexpensive H8/3672 made by Renesas that has built in AD converters and PWM logic generators. The proposed digital controller is applied to a flyback converter that is designed to output DC 5[V] from DC 20∼30[V] and is remotely controlled to make variable outputs from DC 0[V] to 5[V] above in PC. The PWM controller adopts the PD controller in PID. In the last, the response characteristics of a step reference voltage and in a steady state are experimented to verify the feasibility and the usefulness of the proposed flyback converter that is implemented inexpensively.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.2
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• pp.61-69
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• 2003

In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.

• Journal of Digital Convergence
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• v.11 no.2
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• pp.205-214
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• 2013

Team collaboration is becoming commonplace and it is spotlighted in agile software development projects as well. More efficient teamwork in terms of effective team operation and project performance is very important. Heuristic software development staffing method has been used, but algorithm approach is needed to compensate for it. In this paper, we propose a mathematical approaches for staffing developers in teamwork-based software development projects. This consist of six process, and activities in each processor is defined as a mathematical function placement, and functional deployment matrix is used. A case study is presented in order to prove the usefulness of this approach. This paper is a significant research because a mathematical approach of work assignment is developed for human resources by quantitative logic and it deviate from intuitive or heuristic methods used previously.