• Journal of Power Electronics
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• 제17권3호
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• pp.821-834
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• 2017

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.