• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.

• 전자공학회논문지
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• 제50권11호
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• pp.64-69
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• 2013

본 논문에서는 10-bit 해상도의 Two-Step Single-Slope A/D 변환기를 이용한 고속 CMOS Image Sensor(CIS)를 제안하였다. 제안하는 A/D 변환기는 5-bit coarse ADC 와 6-bit fine ADC 로 구성되어 있으며, 기존의 Single-Slope A/D 변환기보다 10배 이상의 변환속도를 나타내었다. 또한 고속 동작에서 적은 노이즈 특성을 갖기 위해 Digital Correlated Double Sampling(D-CDS) 회로를 제안하였다. 설계된 A/D 변환기는 0.13um 1-poly 4-metal CIS 공정으로 제작되었으며 QVGA($320{\times}240$)급 해상도를 갖는다. 제작된 칩의 유효면적은 $5mm{\times}3mm$ 이며 3.3V 전원전압에서 약 35mW의 전력소모를 나타내었다. 변환속도는 10us 이었으며, 프레임율은 220 frames/s으로 측정되었다.

• 한국정보전자통신기술학회논문지
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• 제16권6호
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• pp.465-471
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• 2023

본 논문은 CMOS Image Sensor(CIS)에 사용되는 single-slope ADC(SS-ADC)의 노이즈와 출력의 지연을 개선한 비교기 구조를 제안한다. 노이즈와 출력의 지연 특성을 개선하기 위해 비교기의 첫 번째 단의 출력 노드와 두 번째 단의 출력 노드 사이에 커패시터를 삽입하여 miller effect를 이용한 비교기 구조를 설계하였다. 제안하는 비교기 구조는 작은 capacitor를 이용하여 노이즈와 출력의 지연 및 layout 면적을 개선하였다. Single slop ADC에서 사용되는 CDS 카운터는 T-filp flop과 bitwise inversion 회로를 사용하여 설계하였고 전력 소모와 속도가 개선되었다. 또한 single slop ADC는 analog correlated double sampling(CDS)와 digital CDS를 함께 동작하는 dual CDS를 수행한다. Dual CDS를 수행함으로써 fixed pattern noise(FPN), reset noise, ADC error를 줄여 이미지 품질이 향상된다. 제안하는 comparator 구조가 사용된 single-slope ADC는 0.18㎛ CMOS 공정으로 설계되었다.

• 센서학회지
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• 제27권2호
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• 센서학회지
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• 제14권4호
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• pp.272-277
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• 2005

A CMOS active pixel sensor has been designed and fabricated using standard 2-poly and 4-metal $0.35{\mu}m$ CMOS processing technology. The CMOS active pixel sensor has been made up of a unit pixel having a highly sensitive PMOSFET photo-detector and electronic shutters that can control the light exposure time to the PMOSFET photo-detector, correlated-double sampling (CDS) circuits, and an 8-bit two-step flash analog to digital converter (ADC) for digital output. This sensor can obtain a stable photo signal in a wide range of light intensity. It can be realized with a special function of an electronic shutter which controls the light exposure-time in the pixel. Moreover, this sensor had obtained the digital output using an embedded ADC for the system integration. The designed and fabricated image sensor has been implemented as a $128{\times}128$ pixel array. The area of the unit pixel is $7.60{\mu}m{\times}7.85{\mu}m$ and its fill factor is about 35 %.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.83-91
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• 2014

This paper presents a capacitive readout circuit for tri-axes microaccelerometer with sub-fF offset calibration capability. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a charge-storing capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous offset cancelling circuit using series-connected capacitor arrays. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and $230{\mu}A$, respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are $349{\mu}g$/${\sqrt}$Hz, $341{\mu}g$/${\sqrt}$Hz and $411{\mu}g$/${\sqrt}$Hz, respectively.