• 전기학회논문지
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• 제60권2호
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• pp.320-324
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• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• 전자공학회논문지A
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• 제33A권6호
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• 한국측량학회:학술대회논문집
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• 한국측량학회 2004년도 춘계학술발표회논문집
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• pp.183-195
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• 2004

Photogrammetry is one of the most important sources of GIS application. Nowadays, color photos are used and camera is integrated with GPS/INS sensors. However the photos are still taken from analogue camera and scanned for digital image. For the convenient and accurate image application especially for 3D, airborne digital camera images is essential. In this paper, digital image calibration process with GPS/INS and its accuracy evaluation was presented.

• Nuclear Engineering and Technology
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• 제50권1호
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• pp.203-210
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• 2018

As the modernization of the nuclear instrumentation system progresses, research reactors have adopted digital wide-range neutron power measurement (DWRNPM) systems. These systems typically monitor the neutron flux across a range of over 10 decades. Because neutron detectors only measure the local neutron flux at their position, the local neutron flux must be converted to total reactor power through calibration, which involves mapping the local neutron flux level to a reference reactor power. Conventionally, the neutron power range is divided into smaller subranges because the neutron detector signal characteristics and the reference reactor power estimation methods are different for each subrange. Therefore, many factors should be considered when preparing the calibration procedure for DWRNPM channels. The main purpose of this work is to serve as a reference for performing the calibration of DWRNPM systems in research reactors. This work provides a comprehensive overview of the calibration of DWRNPM channels by describing the configuration of the DWRNPM system and by summarizing the theories of operation and the reference power estimation methods with their associated calibration procedure. The calibration procedure was actually performed during the commissioning of an open-pool type research reactor, and the results and experience are documented herein.

• 전기전자학회논문지
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• 제7권2호
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• pp.245-252
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• 2003

디지털 보정 기능을 갖는 CMOS 압력 센서의 인터페이스 회로를 설계하였다. 인터페이스 회로는 아날로그 부분과 디지털 부분으로 구성되어 있다. 아날로그 부분은 센서로부터 발생한 약한 신호를 증폭시키는 역할을 담당하고 디지털 부분은 온도 보상 및 오프셋 보정 기능을 담당하며 센서 칩과 보정을 조정하는 마이크로컨트롤러와의 통신을 담당한다. 디지털 부분은 I2C 직렬 인터페이스, 메모리, 트리밍 레지스터 및 제어기로 구성된다. I2C 직렬 인터페이스는 IO 핀 수 및 실리콘 면적 면에서 실리콘 마이크로 센서의 요구에 맞게 최적화 되었다. 이 설계의 주요 부분은 최적화된 I2C 프로토콜을 구현하는 제어 회로를 설계하는 것이다. 설계된 칩은 IDEC의 MPW를 통하여 제작되었다. 칩의 테스트를 위하여 테스트 보드를 제작하였으며 테스트 결과 예상한대로 디지털 보정기능이 잘 수행됨을 확인하였다.

• Ocean Systems Engineering
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• 제1권3호
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• pp.195-205
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• 2011

A method for calibrating a laser profiling system for seafloor micro-topography measurements is described. The system consists of a digital camera and an arrangement of six red lasers that are mounted as a unit on a remotely operated vehicle (ROV). The lasers project as parallel planes onto the seafloor, creating profiles of the local topography that are interpreted from the digital camera image. The goal of the calibration was to determine the plane equations for the six lasers relative to the camera. This was accomplished in two stages. First, distortions in the digital image were corrected using an interpolation method based on a virtual pinhole camera model. Then, the laser planes were determined according to their intersections with a calibration target. The position and orientation of the target were obtained by a registration process. The selection of the target shape and size was found to be critical to a successful calibration at sea, due to the limitations in the manoeuvrability of the ROV.

• 디지털산업정보학회논문지
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• 제13권3호
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• 디지털산업정보학회논문지
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• 제9권3호
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• pp.59-65
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• 2013

This paper presents a novel calibration method for a base station system adopting an antenna array. The proposed technique utilizes Zadoff-Chu sequence, which is included in the LTE pilot signal periodically, in order to compute the phase characteristic of each antenna channel. As the Zadoff-Chu sequence exhibits an excellent autocorrelation characteristic, it is possible for the receiving base station to retrieve the Zadoff-Chu sequence transmitted from each mobile terminal. In addition, we can obtain the phase characteristic of each antenna channel, which is the ultimate goal of the calibration procedure. The proposed calibration algorithm has been implemented using an FPGA (Field Programmable Gate Array). We have applied the proposed algorithm to an array consisting of 2 antenna elements for simplicity. the phase value implied to the first and second antenna path is very accurately calculated from the proposed procedure. From the experimental test, the proposed method provides accurate calibration results.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Journal of Astronomy and Space Sciences
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• 제19권4호
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• pp.293-304
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• 2002

본 논문에서는 2002년 하반기에 발사 예정인 과학로켓 3호에 탑재되어 있는 자력계의 비행모델(flight model) 제작 모델의 디지털 회로 설계와 부품선정 및 Fluxgate 자력계 AIM(Attitude Information Magnetometer)과 지구 자기장 섭동 측정용 Search-Coil 자력계 SIM(Scientific Investigation Magnetometer)의 검교정시험 수행 결과에 대해 기술하였다. 초기 설계된 자력계 디지털 회로는 자료의 샘플링 속도가 낮고, 잡음이 많이 발생되어 이를 향상시켰으며, 자료의 신뢰성을 확보하기 위해 부품 재선정 및 회로를 다시 설계하였다. 재구성이후 자력계의 디지털 검교정시험을 실시하였고, 그 결과, 최초 아날로그 검교정시험때 설정한 AIM 센서의 InT의 분해능보다 실제 측정된 분해능 값이 떨어졌음을 확인할 수 있었다. 이를 보정하기 위해 수치계산법을 이용하여 보정치와 오차값을 계산하였으며, 이 보정치들을 과학로켓 3호 발사 이후 얻어지는 자력계 자료에 적용할 예정이다.