• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.5
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• pp.860-865
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• 2010

When a circuit breaker is opened, a large capacitance around the buses, the circuit breaker and the potential transformer (PT) might cause PT ferroresonance. During PT ferroresonance, the iron core repeats saturation and unsaturation even though the supplied voltage is a rated voltage. This paper describes an analytical analysis of PT ferroresonance in the transient-state. To analyze ferroresonance analytically, the iron core is modelled by a simplified two-segment core model in this paper. Thus, a nonlinear ordinary differential equation (ODE) for the flux linkage is changed into a linear ODE with constant coefficients, which enables an analytical analysis. In this simplified model, each state, which is either saturated or unsaturated state, corresponds to one of the three modes, i.e. overdamping, critical damping and underdamping. The flux linkage and the voltage in each state are obtained analytically by solving the linear ODE with constant coefficients. The proposed transient analysis is effective in the more understanding of ferroresonance and thus can be used to design a ferroresonance prevention or suppression circuit of a PT.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1879-1881
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• 1998

The conducted differential mode (DM) EMI in a flyback converter are analyzed. Circuit modeling of passive components and PCB pattern for the EMI simulation are presented. Using the model, high frequency noise path is analyzed. The analyses are verified with simulations by identifying the peakings of the EMI pattern.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.1-6
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• 2005

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for LCD driver IC. In the proposed circuit, we apply a couple of primitive data to DLVDS circuit as inputs. The transmitter converts two inputs to two kinds of fully differential level signals. In this circuit, two transmission lines are sufficient to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers The original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25\mu m$ CMOS technology. The resultant circuit shows 1-Gbps/2-line data rate and 35-mW power consumption at 2.5V supply voltage, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.1
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• pp.46-51
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• 1991

The new signal process circuit using ISFETs as two input devices of a MOS differential amplifier stage for application to a ISFET biosensor was developed and its operational characteristics simulated. For a single chip integration of ISFETs, developed signal process circuit and metal reference electrode, serial studies including process development and chip layout was carried out.

• Proceedings of the KIEE Conference
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• 1999.07a
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• pp.369-371
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• 1999

The post-arc current in VCB(Vacuum Circuit Breaker) was calculated from the transient recovery voltage. A differential equation for the post-arc current was derived from the equivalent circuit of the test circuit. And it's results were showed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.91-99
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• 1994

We used CMOS current mirror and differenial amplifier to find out how the degradation of each devices in circuit affect total circuit performance. The devices in circuit wer degraded by hot-carrier generated during circuit operation and total circuit performance were changed according to the change of each device parameters. To examine the circuit performance phenomena of current mirror, we analyzed three diffent kinds of current mirrors and made correlation model between circuit performance and stressed device parameters, and compare hot-carrier immunity of these circuits. Also we analyzed how the performance of differential amplifier degraded from the initial value after hot-carrier stress incircuit operations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.761-764
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• 2007

This paper addresses the analysis and the design optimization of differential interconnects for Low-Voltage Differential Signaling (LVDS) applications. Thanks to the differential transmission and the low voltage swing, LVDS offers high data rates and improved noise immunity with significantly reduced power consumption in data communications, high-resolution display, and flat panel display. We present an improved model and new equations to reduce impedance mismatch and signal degradation in cascaded interconnects using optimization of interconnect design parameters such as trace width, trace height and πace space in differential flexible printed circuit board (FPCB) transmission lines. We have carried out frequency-domain full-wave electromagnetic simulations, time-domain transient simulations, and S-parameter simulations to evaluate the high-frequency characteristics of the differential FPCB interconnects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.61-66
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• 2011

A new via structure on printed circuit board has been proposed for differential signaling in applications of high-speed interconnection. In new structure, the via is physically separated and then divided into two electrically-isolated sections using mechanical drill routing process. These cutted vias are connected respectively to the traces of the differential pair. New via structure makes possible to rout the differential pair using only one via, while conventional via structure needs two vias for interconnection. Because the spacing even in via region keeps almost constant, new via structure can alleviate an impedance discontinuity and then enhance its signal transmission characteristics such as reflection loss and insertion loss. It is expected that new via structure is effective in differential signaling for high-speed interconnection.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.5
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• Journal of the Korean Society of Industry Convergence
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• v.3 no.2
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• pp.149-154
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• 2000

The purpose of this study is to measure the compression temperature in cylinder by using the fine thermocouple. As for using the thermocouple, it's response time delay should be regarded, even if it is a fine one. So, the output of thermocouple needs some compensation. The compensation circuit, which consists of a differential and an adding circuit is used for the compensate the time lag. And the time constant of the compensation circuit is determined the time between the TDC and the maximum point of the thermocouple output. Using this compensation circuit, the compression temperature is investigated of the cylinder in the diesel engine.