• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.176-176
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• 2010

One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio (Ion/Ioff), leakage current, threshold voltage, and hysteresis under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stability of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers was investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic-layer-deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to 105 times with 5mm bending radius. In the most of the devices after 105 times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the Ion/Ioff and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

• The Journal of Engineering Geology
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• v.25 no.3
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• pp.349-356
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• 2015

Although geophysical methods are useful and generally provide valuable information about the subsurface, it is important to recognize their limitations. A common limitation is the lack of sufficient contrast in physical properties between different layers. Thus, multiple methods are commonly used to best constrain the physical properties of different layers and interpret each section individually. Ground penetrating radar (GPR) and shallow seismic reflection (SSR) methods, used for shallow and very shallow subsurface imaging, respond to dielectric and velocity contrasts between layers, respectively. In this study, we merged GPR and SSR data from a test site within the Cheongui granitic mass, where the water table is ~3 m deep all year. We interpreted the data in combination with field observations and existing data from drill cores and well logs. GPR and SSR reflections from the tops of the sand layer, water table, and weathered and soft rocks are successfully mapped in a single section, and they correlate well with electrical resistivity data and SPS (suspension PS) well-logging profiles. In addition, subsurface interfaces in the integrated section correlate well with S-wave velocity structures from multi-channel analysis shear wave (MASW) data, a method that was recently developed to enhance lateral resolution on the basis of CMP (common midpoint) cross-correlation (CMPCC) analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.765-770
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• 2001

Metal-ferroelectric-insulator- semiconductor(MFTS) devices by using rapid thermal annealed (RTA) LiNbO$_3$/AIN/Si(100) structures were successfully fabricated and demonstrated nonvolatile memory operations. Metal-insulator-semiconductor(MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2 V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/$\textrm{cm}^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8 V, 50 % duty cycle) in the 500 kHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.278.1-278.1
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• 2014

Organic materials have been explored as the gate dielectric layers in thin film transistors (TFTs) of backplane devices for flexible display because of their inherent mechanical flexibility. However, those materials possess some disadvantages like low dielectric constant and thermal resistance, which might lead to high power consumption and instability. On the other hand, inorganic gate dielectrics show high dielectric constant despite their brittle property. In order to maintain advantages of both materials, it is essential to develop the alternative materials. In this work, we manufactured nanocomposite gate dielectrics composed of organic material and inorganic nanoparticle and integrated them into organic TFTs. For synthesis of nanocomposite gate dielectrics, polyimide (PI) was explored as the organic materials due to its superior thermal stability. Candidate nanoprticles (NPs) of halfnium oxide, titanium oxide and aluminium oxide were considered. In order to realize NP concentration dependent electrical characteristics, furthermore, we have synthesized the different types of nanocomposite gate dielectrics with varying ratio of each inorganic NPs. To analyze gate dielectric properties like the capacitance, metal-Insulator-metal (MIM) structures were prepared together with organic TFTs. The output and transfer characteristics of organic TFTs were monitored by using the semiconductor parameter analyzer (HP4145B), and capacitance and leakage current of MIM structures were measured by the LCR meter (B1500, Agilent). Effects of mechanical cyclic bending of 200,000 times and thermally heating at $400^{\circ}C$ for 1 hour were investigated to analyze mechanical and thermal stability of nanocomposite gate dielectrics. The results will be discussed in detail.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.2
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• pp.83-88
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• 2017

In this paper, TE(transverse electric) scattering problems by a conductive strip grating between a double dielectric layer are analyzed by applying the PMM(point matching method) known as a numerical method of electromagnetic fileld. The boundary conditions are applied to obtain the unknown field coefficients, the scattered electromagnetic fields are expanded in a series of Floquet mode functions, and the conductive boundary condition is applied to analysis of the conductive strip. The numerical results for the normalized reflected and transmitted power are analyzed by according as the width and spacing of conductive strip, the relative permittivity and thickness of the double dielectric layers, and incident angles. The most normalized reflected powers of the sharp variations in minimum values are scattered in direction of the other angles except incident angle. The numerical results for the presented structure of this paper are shown in good agreement compared to those of the existing papers.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.3
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• pp.424-430
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• 1998

Film characteristics of thin ONO dielectric layers for MONOS (metal-oxide-nitride-oxide-semiconductor) EEPROM was investigated by AES, SIMS, TEM and AFM. The ONO films with different dimension of tunneling oxide, nitride, and blocking oxide were fabricated. During deposition of the LPCVD nitride films on tunneling oxide, this thin oxide was nitrized. When the blocking oxide were deposited on the nitride film, the oxygen not only oxidized the nitride surface, but diffused through the nitride. The results of ONO film analysis exhibits that it is made up of $SiO_2$(blocking oxide)/O-rich SiOxNy (interface)/ N-rich SiOxNy(nitride)/O-rich SiOxNy(tunneling oxide). In addition, the SiON phase is distributed mainly near the tunneling oxide/nitride and nitride/blocking oxide interfaces, and the $Si_2NO$ phase is distributed mainly at nitride side of each interfaces and in tunneling oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.349-349
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• 2008

유비쿼터스 시대를 맞이하여 현재의 전자제품은 고주파 환경에서의 소형화된 마이크로파 소자를 요구하고 있다. 현재 구현되고 있는 마이크로파 소자의 형태는 여러 가지 전송선로 중에 하나로서 금속의 그라운드면 위에 유전체 막을 형성하고 그 위에 금속선을 정밀하게 패터닝하여 각 종 소자를 연결하는 microstrip line의 형태가 많이 사용된다. 이러한 microstrip line 형태의 소자를 설계할 시에 소자 자체의 구조나 유전체 막이 그 소자의 성능을 크게 좌우한다. 여기서 유전체 막은 신호선과 그라운드면 간의 전자파를 집중시켜주어 방사손실을 줄여주는 역할을 한다. 유전체 막의 두께는 소자의 전체적인 크기를 결정하는 요인이 된다. 이는 유전체 막의 두께가 감소할 경우 50 $\Omega$ 임피던스 매칭을 위해 막 위에 형성되는 소자들의 선폭도 동시에 줄여야 하므로 소자의 소형화도 가능 하여진다. 하지만 유전체 막의 두께가 감소할 경우 전자파가 유전체 막에 집중되지 못하여 방사손실이 커지게 되고 소자의 성능이 저하된다. 이런 점을 고려할 때 소자의 소형화를 만족시키면서 동시에 소자의 성능을 유지할 수 있는 유전체 막의 최적화 두께에 대한 연구가 필요하다. 볼 연구에서는 유전체 막의 최적화 두께를 제시하기 위해 대표적 마이크로파 소자인 Edge-Coupled Filter에 대하여 3-D Electromagnetic Simulator로 설계하고 유전체 막의 두께와 Filter 성능 간의 관계를 연구하였다. Filter의 성능은 유지하도록 하면서 유전체 막의 두께를 감소시켜 나간 결과, 약 30 ~ 40 ${\mu}m$ 의 최적화 두께를 얻을 수 있었다. 한편 30 ~ 40 ${\mu}m$ 두께의 후막 공정을 고려할 때 기존의 성막공정으로는 성막시간, 공정의 난이도, 공정온도 등의 면에서 난점이 존재하며 이러한 점들을 극복할 수 있는 Aerosol Deposition Method의 적용 가능성에 대해서 연구하였다.