• Title/Summary/Keyword: Device to Device (D2D)

Search Result 1,734, Processing Time 0.032 seconds

Interface trap density distribution in 3D sequential Integrated-Circuit and Its effect (3차원 순차적 집적회로에서 계면 포획 전하 밀도 분포와 그 영향)

  • Ahn, TaeJun;Lee, Si Hyun;Yu, YunSeop
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.19 no.12
    • /
    • pp.2899-2904
    • /
    • 2015
  • This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

A 8b 1GS/s Fractional Folding-Interpolation ADC with a Novel Digital Encoding Technique (새로운 디지털 인코딩 기법을 적용한 8비트 1GS/s 프랙셔널 폴딩-인터폴레이션 ADC)

  • Choi, Donggwi;Kim, Daeyun;Song, Minkyu
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.50 no.1
    • /
    • pp.137-147
    • /
    • 2013
  • In this paper, an 1.2V 8b 1GS/s A/D Converter(ADC) based on a folding architecture with a resistive interpolation technique is described. In order to overcome the asymmetrical boundary-condition error of conventional folding ADCs, a novel scheme with an odd number of folding blocks and a fractional folding rate are proposed. Further, a new digital encoding technique with an arithmetic adder is described to implement the proposed fractional folding technique. The proposed ADC employs an iterating offset self-calibration technique and a digital error correction circuit to minimize device mismatch and external noise The chip has been fabricated with a 1.2V 0.13um 1-poly 6-metal CMOS technology. The effective chip area is $2.1mm^2$ (ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$) and the power dissipation is about 350mW including calibration engine at 1.2V power supply. The measured result of SNDR is 46.22dB, when Fin = 10MHz at Fs = 1GHz. Both the INL and DNL are within 1LSB with the self-calibration circuit.

Development of weight prediction 2D image technology using the surface shape characteristics of strawberry cultivars

  • Yoo, Hyeonchae;Lim, Jongguk;Kim, Giyoung;Kim, Moon Sung;Kang, Jungsook;Seo, Youngwook;Lee, Ah-yeong;Cho, Byoung-Kwan;Hong, Soon-Jung;Mo, Changyeun
    • Korean Journal of Agricultural Science
    • /
    • v.47 no.4
    • /
    • pp.753-767
    • /
    • 2020
  • The commercial value of strawberries is affected by various factors such as their shape, size and color. Among them, size determined by weight is one of the main factors determining the quality grade of strawberries. In this study, image technology was developed to predict the weight of strawberries using the shape characteristics of strawberry cultivars. For realtime weight measurements of strawberries in transport, an image measurement system was developed for weight prediction with a charge coupled device (CCD) color camera and a conveyor belt. A strawberry weight prediction algorithm was developed for three cultivars, Maehyang, Sulhyang, and Ssanta, using the number of pixels in the pulp portion that measured the strawberry weight. The discrimination accuracy (R2) of the weight prediction models of the Maeyang, Sulhyang and Santa cultivars was 0.9531, 0.951 and 0.9432, respectively. The discriminative accuracy (R2) and measurement error (RMSE) of the integrated weight prediction model of the three cultivars were 0.958 and 1.454 g, respectively. These results show that the 2D imaging technology considering the shape characteristics of strawberries has the potential to predict the weight of strawberries.

The Development and Implementation of Model-based Control Algorithm of Urea-SCR Dosing System for Improving De-NOx Performance and Reducing NH3-slip (Urea-SCR 분사시스템의 DeNOx 저감 성능 향상과 NH3 슬립저감을 위한 모델 기반 제어알고리즘 개발 및 구현)

  • Jeong, Soo-Jin;Kim, Woo-Seung;Park, Jung-Kwon;Lee, Ho-Kil;Oh, Se-Doo
    • Transactions of the Korean Society of Automotive Engineers
    • /
    • v.20 no.1
    • /
    • pp.95-105
    • /
    • 2012
  • The selective catalytic reduction (SCR) system is a highly-effective aftertreatment device for NOx reduction of diesel engines. Generally, the ammonia ($NH_3$) was generated from reaction mechanism of SCR in the SCR system using the liquid urea as the reluctant. Therefore, the precise urea dosing control is a very important key for NOx and $NH_3$ slip reduction in the SCR system. This paper investigated NOx and $NH_3$ emission characteristics of urea-SCR dosing system based on model-based control algorithm in order to reduce NOx. In the map-based control algorithm, target amount of urea solution was determined by mass flow rate of exhaust gas obtained from engine rpm, torque and $O_2$ for feed-back control NOx concentration should be measured by NOx sensor. Moreover, this algorithm can not estimate $NH_3$ absorbed on the catalyst. Hence, the urea injection can be too rich or too lean. In this study, the model-based control algorithm was developed and evaluated on the numerical model describing physical and chemical phenomena in SCR system. One channel thermo-fluid model coupled with finely tuned chemical reaction model was applied to this control algorithm. The vehicle test was carried out by using map-based and model-based control algorithms in the NEDC mode in order to evaluate the performance of the model based control algorithm.

Fabrication and measurement of RH/LH mode-switchable CRLH transmission line based on silicon RF MEMS switches (실리콘 RF MEMS 스위치 기반의 RH/LH 모드 스위칭이 가능한 CRLH 전송선 제작 및 측정)

  • Hwang, Sung-Hyun;Jang, Tae-Hee;Bang, Yong-Seung;Kim, Jong-Man;Kim, Yong-Kweon;Lim, Sung-Joon;Baek, Chang-Wook
    • Proceedings of the KIEE Conference
    • /
    • 2009.07a
    • /
    • pp.1507_1508
    • /
    • 2009
  • This study proposes a composite right/left-handed transmission line (CRLH-TL) that permits switching between the right-handed (RH) and left-handed (LH) modes using single crystalline silicon (SCS) RF MEMS switches. It is possible to change modes from the RH to LH mode, or vice versa, by controlling the admittance of capacitors and the impedance of inductors using switch operations. The proposed switchable CRLH-TL consists of SCS RF MEMS switches, metal-insulator-metal (MIM) capacitors and shunt inductors. At 8 GHz, the fabricated device shows a phase response of $87^{\circ}$ with an insertion loss of 2.7 dB in the LH mode, and a phase response of $-77^{\circ}$ with an insertion loss of 0.56 dB in the RH mode.

  • PDF

Fabrication and characterization of PbIn-Au-PbIn superconducting junctions

  • Kim, Nam-Hee;Kim, Bum-Kyu;Kim, Hong-Seok;Doh, Yong-Joo
    • Progress in Superconductivity and Cryogenics
    • /
    • v.18 no.4
    • /
    • pp.5-8
    • /
    • 2016
  • We report on the fabrication and measurement results of the electrical transport properties of superconductor-normal metal-superconductor (SNS) weak links, made of PbIn superconductor and Au metal. The maximum supercurrent reaches up to ${\sim}6{\mu}A$ at T = 2.3 K and the supercurrent persists even at T = 4.7 K. Magnetic field dependence of the critical current is consistent with a theoretical fit using the narrow junction model. The superconducting quantum interference device (SQUID) was also fabricated using two PbIn-Au-PbIn junctions connected in parallel. Under perpendicular magnetic field, we clearly observed periodic oscillations of dV/dI with a period of magnetic flux quantum threading into the supercurrent loop of the SQUID. Our fabrication methods would provide an easy and simple way to explore the superconducting proximity effects without ultra-low-temperature cryostats.

A Study on Folded Monopole Antenna with Spiral Shape for Wireless DVI Dongle Applications (무선 DVI 동글장치를 위한 스파이럴 구조를 갖는 폴디드 모노폴 안테나에 관한 연구)

  • Lee, Jae-Choon;Lee, Yun-Min
    • The Transactions of the Korean Institute of Electrical Engineers P
    • /
    • v.65 no.1
    • /
    • pp.72-75
    • /
    • 2016
  • In this paper, we proposes a internal antenna for wireless DVI dongle device using the folded monopole structure. The proposed antenna uses a basic structure of spiral and monopole. The antenna optimized for parameters length, gap, width, and rectangle of folded monopole antenna using the spiral structure. To confirm the characteristics of the antenna parameters, HFSS from ANSYS Inc. was used for the analysis. We used an FR4 dielectric substrate with a dielectric constant of 4.4. The DVI dongle size of the proposed antenna is $50{\times}40{\times}1.6mm$, and the size of the antenna area is $10{\times}40mm$. There is a value of return loss less then -10dB in 2.4GHz and 5.8GHz, band and the maximum antenna gain is -4.13dBi. The utilization possibility of the wireless DVI Dongle antenna have a folded monopole with spiral shape could be confirmed according to compare and analyze the simulation and measurement data.

Development of 3300V 1MVA Multilevel Inverter using Cascaded H-Bridge Cell (3300V 1MVA H-브릿지 멀티레벨 인버터 개발)

  • Park Y.M.;Kim Y.D.;Lee H.W.;Lee S.H.;Seo K.D.
    • Proceedings of the KIPE Conference
    • /
    • 2003.07b
    • /
    • pp.593-597
    • /
    • 2003
  • Multilevel power conversion technology has received increasing attention recently for high power applications. The converters with the technology are suitable for high voltage and high power applications due to their ability to synthesize waveforms with better harmonic spectrum and apply for the high voltage equipment with a limited voltage rating of device. In the family of multilevel inverters, the topologies based on cascaded H-bridges are particularly attractive because of their modularity and simplicity of control. This paper presents multilevel inverter with cascaded H-bridge for large-power motor drives. The main features of this drive 1) reduce harmonic injection 2) can generate near-sinusoidal voltages, 3) have almost no common-mode voltage; 4) are low dv/dt at output voltage; 5)do not generate significant over-voltage on motor terminal; The topology of the developed product is presented and the feasibility study of the inverter on 3300v 1MVA 7-level H-bridge type was tarried out with experiments.

  • PDF

A Compact Model of Gate-Voltage-Dependent Quantum Effects in Short-Channel Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

  • Kim, Ji-Hyun;Sun, Woo-Kyung;Park, Seung-Hye;Lim, Hye-In;Shin, Hyung-Soon
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.11 no.4
    • /
    • pp.278-286
    • /
    • 2011
  • In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.

Design of a PC based Real-Time Software GPS Receiver (PC기반 실시간 소프트웨어 GPS 수신기 설계)

  • Ko, Sun-Jun;Won, Jong-Hoon;Lee, Ja-Sung
    • The Transactions of the Korean Institute of Electrical Engineers D
    • /
    • v.55 no.6
    • /
    • pp.286-295
    • /
    • 2006
  • This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.