• 제목/요약/키워드: Device fabrication

검색결과 1,417건 처리시간 0.03초

SMES용 초전도마그네트 제작 및 특성시험 (Test and Fabrication of the Superconducting Magnet for a SMES)

  • 김해종;성기철;조전욱;권영길;류강식;류경우
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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    • pp.6-8
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    • 2001
  • This paper describes the design, fabrication and experimental results for the 1MJ SMES magnet made by using the design code of a SMES device that we developed. The inductance and field measurements indicate that the developed code is applicable to the design of a SMES device. The test results show that the magnet is excellent in comparison with previously fabricated magnets outside.

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Flexible Ultra-high Gas Barrier Substrate for Organic Electronics

  • Yan, Min;Erlat, Ahmet Gun;Zhao, Ri-An;Scherer, Brian;Jones, Cheryl;Smith, David J.;McConnelee, Paul A.;Feist, Thomas;Duggal, Anil
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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    • pp.445-446
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    • 2007
  • The use of plastic substrates enables new applications, such as flexible display devices, and other flexible electronic devices, using low cost, rollto-roll (R2R) fabrication technologies. One of the limitations of polymeric substrate in these applications is that oxygen and moisture rapidly diffuse through the material and subsequently degrade the electro-optical devices. GE Global Research (GEGR) has developed a plastic substrate technology comprised of a superior high-heat polycarbonate (LEXAN(R)) substrate film and a unique transparent coating package that provides the ultrahigh barrier (UHB) to moisture and oxygen, chemical resistance to solvents used in device fabrications, and a high performance transparent conductor. This article describes the coating solutions for polycarbonate (LEXAN(R)) films and its compatibility with OLED device fabrication processes.

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SMES용 초전도코일 제작 및 특성시험 (Test and Fabrication of the Superconducting Coil for a SMES)

  • 김해종;성기철;조전욱;배준한;김석환;권영길;류경우;김상현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 하계학술대회 논문집 B
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    • pp.879-881
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    • 2003
  • For quite a long time various researches and developments of superconducting magnetic energy storage(SMES) device for enhancement of power quality control of sensitive electric toad. This paper describes the design, fabrication and experimental results for the 3MJ SMES magnet made by using the design code of a SMES device that we developed. A computer code was developed to find the parameters of the SMES magnet which has minimum amount of superconductors for the same stored energy, and the 3MJ SMES magnet was designed based upon that.

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고휘도 발광을 위한 유기 EL 소자 제작 (The fabrication of organic EL device for high contrast)

  • 여철호;손철호;박정일;장선주;박종화;이영종;정홍배
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 추계학술대회 논문집
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    • pp.166-169
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    • 2000
  • The Organic Electroluminescence (OEL) device, that was consisted of ALq3(8-hydroxyquinoline aluminum) and TPD(N,N'-diphenyl-N,N'-bis(3-methylphenyl)-1,1'-biphenyl-4,4'-diamine), has been used. We investigated characteristics of brightness and current density about OEL that was oxidated each layers. We used two samples that were fabricated each continuous and non-continuous method. Emission was observed above 10mA/$\textrm{cm}^2$ and luminance was measured to be 1530cd/$\textrm{cm}^2$ at a current density of 100mA/$\textrm{cm}^2$. A luminance of over 2600cd/$\textrm{cm}^2$ was also observed after the final fabrication process.

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반도체 제조공정의 Critical Dimension 변동에 대한 통계적 분석 (Statistical Analysis on Critical Dimension Variation for a Semiconductor Fabrication Process)

  • 박성민;이정인;김병윤;오영선
    • 산업공학
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    • 제16권3호
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    • pp.344-351
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    • 2003
  • Critical dimension is one of the most important characteristics of up-to-date integrated circuit devices. Hence, critical dimension control in a semiconductor wafer fabrication process is inevitable in order to achieve optimum device yield as well as electrically specified functions. Currently, in complex semiconductor wafer fabrication processes, statistical methodologies such as Shewhart-type control charts become crucial tools for practitioners. Meanwhile, given a critical dimension sampling plan, the analysis of variance technique can be more effective to investigating critical dimension variation, especially for on-chip and on-wafer variation. In this paper, relating to a typical sampling plan, linear statistical models are presented for the analysis of critical dimension variation. A case study is illustrated regarding a semiconductor wafer fabrication process.

LIGA 공정을 이용한 평면형 광소자용 Ni 마스터 제작 (Fabrication of Ni master for the replication of planar optical devices by LIGA process)

  • 김진태;정명영
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2003년도 춘계학술대회
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    • pp.945-949
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    • 2003
  • LIGA(Lithographie Galvanoformung Abformung), a fabrication method for the production of microstructrues with a high aspect ratio, is now playing an important role in a fabrication of polymeric optical waveguide device as the replication processes have been developed such as hot embossing and injection molding. The present report deals with the fabrication of Ni master used for the replication of multi-mode polymeric optical waveguide. With the basic technological features in the sequence of the LIGA technique, we fabricated Ni master with 12 channel microstructures of $100\;{\times}\;100{\mu}m\;^2{\times}\;60mm$, and achieved an accuracy of ${\pm}1\;{\mu}m$. Manufactured polymeric optical wavegude with the same using hot embossing process has also the same accuracy and approved its mass production capability.

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제조 공정상 랜덤 특성을 고려한 IC 최악조건 해석 (IC Worst Case Analysis Considered Random Fluctuations on Fabrication Process)

  • 박상봉;박노경;전흥우;문대철;차균현
    • 대한전자공학회논문지
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    • 제25권6호
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    • pp.637-646
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    • 1988
  • The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

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Convex 구조를 갖는 MOSFET 소자의 제작 및 그 전기적 특성에 관한 연구 (A Study on the Fabrication of the Convex Structured MOSFET and Its Electrical Characteristics)

  • 김기홍;김현철;김흥식;안철
    • 전자공학회논문지A
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    • 제29A권8호
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    • pp.78-88
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    • 1992
  • To improve the characteristics of sub$\mu$m short channel MOSFET device, a new device having the convex structure is proposed. This device has 3-dimensionally expandable channel length according to the vertical etched silicon height. For the purpose of comparing the DC and AC characteristics, planar device is also fabricated. Comparing the channel length, the convex device with 0.4$\mu$m silicon height is larger about 0.56$\mu$m in NMOS and 0.78$\mu$m in PMOS than planar devices. DC characteristics, such as threshold voltage, operational current, substrate current and breakdown voltage are compared together with AC characteristics using the ring oscillator inverter delay. Also process and device simulation are performed and the differences between convex and pranaldevice are also compared.

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