• Title/Summary/Keyword: Detection Circuit

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The Influence of Energy Density upon Detection Time of Information Signal in AF Track Circuit (AF궤도회로에서 에너지 밀도가 정보신호 검출시간에 미치는 영향)

  • Kim, Min-Seok;Hwang, In-Kwang;Lee, Jong-Woo
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.60 no.6
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    • pp.1146-1151
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    • 2011
  • There are two methods for train control in information transmission by using track circuit system and installing wayside transmitter. Information signal is transmitted to the on-board antenna by using rails. Continuous information about train intervals, speed and route is received by on-board antenna in AF track circuit system. The information signal is included with carrier wave and received by magnetic coupling in the on-board antenna. Therefore, it is important to define standard current level in the AF track circuit system. When current flowed to rails is low, magnetic sensors are not operated by decreasing magnetic field intensity. Hence, SNR is decreased because electric field intensity is decreased. When the SNR is decreased, there is the serious influence of noise upon demodulation. So, the frequency of information signal is not extracted in frequency response. Thus, it is possible to happen to train accident and delay as the information signal is not analyzed in the on-board antenna. In this paper, standard energy density is calculated by using Parseval's theory in UM71c track circuit. Hence, detection time of information signal is presented.

Winding Turn-to-Turn Faults Detection of Fault-Tolerant Permanent-Magnet Machines Based on a New Parametric Model

  • Liu, Guohai;Tang, Wei;Zhao, Wenxiang
    • Journal of international Conference on Electrical Machines and Systems
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    • v.2 no.1
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    • pp.23-30
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    • 2013
  • This paper proposes a parametric model for inter-turn fault detection in a fault-tolerant permanent-magnet (FTPM) machine, which can predict the effect of the short-circuit fault to various physical quantity of the machine. For different faulty operations, a new effective stator inter-turn fault detection method is proposed. Finally, simulations of vector-controlled FTPM machine drives are given to verify the feasibility of the proposed method, showing that even single-coil short-circuit fault could be exactly detected.

A $160{\times}120$ Light-Adaptive CMOS Vision Chip for Edge Detection Based on a Retinal Structure Using a Saturating Resistive Network

  • Kong, Jae-Sung;Kim, Sang-Heon;Sung, Dong-Kyu;Shin, Jang-Kyoo
    • ETRI Journal
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    • v.29 no.1
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    • pp.59-69
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    • 2007
  • We designed and fabricated a vision chip for edge detection with a $160{\times}120$ pixel array by using 0.35 ${\mu}m$ standard complementary metal-oxide-semiconductor (CMOS) technology. The designed vision chip is based on a retinal structure with a resistive network to improve the speed of operation. To improve the quality of final edge images, we applied a saturating resistive circuit to the resistive network. The light-adaptation mechanism of the edge detection circuit was quantitatively analyzed using a simple model of the saturating resistive element. To verify improvement, we compared the simulation results of the proposed circuit to the results of previous circuits.

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The development of 110/220V alternative static output ballast by using passive power factor correction circuit (수동역률 개선회로를 이용한 110/220V 겸용 정출력 안정기 개발)

  • Song, Myung-Suk;Jo, Gye-Hyun;Park, Chong-Yeun
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2004.05a
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    • pp.210-213
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    • 2004
  • In this paper, we propose the passive PFC(Power Factor Correction) circuit of an electronic ballast with the constant power the detection circuit for 110 or 220 volt. The proposed PFC circuit is composed with the modified dither circuit and the input voltage detection circuit. We have concluded that the proposed method is the attractive method to improve of power factor for the electronic ballast with the input voltage regulation and it is a similar experimental results with other active power factor correction method using other PWM ICs.

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The Circuit design for Neutron Detection (중성자 검출을 위한 회로설계)

  • Kim, Sang-Jin;Seong, Nak-Jin;Kim, Ki-Joon
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.05b
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    • pp.42-46
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    • 2003
  • In this study, to measure the moisture of compaction, it is designed to use the 2neutron detectors. To perform the optimal design of their circuit, it is planned high voltage generator and voltage stable circuit and they are very suitable for detection demand. Also, it can be count to data calibration excluded count of ripple.

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Testable Design on the Built In Test Method (고장검출이 용이한 Built-In Test 방식의 설계)

  • Seung Ryong Rho
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.24 no.3
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    • pp.535-540
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    • 1987
  • This paper proposes a circuit partitioning method and a multifunctional BILBO which can perform the multimodule test in the case of testing VLSI circuits. By using these circuit partitioning method and multifunctional BILBO, test time and cost can be reduced greatly by performing the pipeline test method. And the quantity of circuit that shold be added for testing is also reduced in half by interposing only one BILBO between each module. Also, we confirmed that the multifunctional BILBO proposed here has high error detection capability by analyzing error detection capability of this multifunctional BILBO in mathematics.

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Novel Method for SiC Mosfet Desatruation Detection Circuit using Nonlinear Block. (Nonlinear Block을 이용한 새로운 방식의 SiC Mosfet Desaturation Detection Circuit)

  • Kim, Sung Jin;Nam, Kwang Hee
    • Proceedings of the KIPE Conference
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    • 2016.11a
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    • pp.226-227
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    • 2016
  • 본 논문은 SiC Mosfet Gate Driver에서 Overcurrent상황 발생시 Mosfet 양단의 전압을 검출함으로써 스위칭 소자를 보호하는 Desaturation detction circuit에 대해 다룬다. IGBT와 다르게 SiC Mosfet의 경우 ohmic 영역과 saturation영역의 구분이 명확하지 않기 때문에 과전류 발생시 Mosfet 양단 전압을 검출하는데 어려움이 있다. 따라서 이를 보완하기 위하여 Mosfet drain측에 새로운 회로를 추가로 설계함으로써 이를 보완하여 효과적으로 양단전압을 검출한다.

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Development of Contaminant Leakage Detection System Using Electrical Resistance Measurement: ll. Evaluation of Applicability for Landfill Site by Field Model Tests (전기저항 측정기법을 이용한 오염물질 누출감지시스템의 개발: II. 현장모형시험을 통한 매립지에의 적용성 평가)

  • 오명학;이주형;박준범;김형석;강우식
    • Journal of the Korean Geotechnical Society
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    • v.17 no.6
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    • pp.225-233
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    • 2001
  • Field model tests were performed to develop the grid-net landfill leachate leakage detection system using electrical resistance. Electric circuit tests were also carried out to investigate the expected electrical effects of grid-net electric circuit. The resistance of leaking point showed lower value than that of non leaking point. Grid-net leakage detection system was thought to be effective to locate the leachate leaking point. The measured electrical resistance along the wire including the leaking point was slightly reduced following the reduction of electrical resistance at the leaking point, which was explained by electric circuit test results.

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A Study on the Rail Rupture Detection by the Return Current (귀선전류를 이용한 레일절손 검지에 관한 연구)

  • KIM, Yong-Kyu;YOON, Yong-Ki;LEE, Jong-Hyun;KWAK, Woo-Hyun;LEE, Kwang-Hee
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.65 no.7
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    • pp.1303-1310
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    • 2016
  • The track circuit carries out a train detection using a electrical closed loop, and incidentally it detects the rail rupture using the track circuit current flowing rail. However, in the case of the axle counter or the Radio based train control system, it requires a new way for detecting the rail rupture because of not using the track circuit. To solve this problem, it periodically checks non-steady state of rail by the track inspection car. but real-time detection of the rail rupture is impossible. Therefore, this paper analyzed feasibility to realize a real-time detection of rail rupture by using the return current.

A Study of a High Performance Capacitive Sensing Scheme Using a Floating-Gate MOS Transistor

  • Jung, Seung-Min
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.194-199
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    • 2012
  • This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.