• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11A
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• pp.909-917
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• 2009

In this paper, we proposed and implemented the method to efficiently generate TDD synchronization signal and the digital circuit for the RF repeater which can eliminate the shadow region in the wireless communication field using the time division duplex (TDD) method. After detecting the TDD signal from the transmitted or received RF signal, the detected TDD signal is fed to the RF repeater for the normal operation. The proposed technique detects the envelop of the downlink signal and amplifies the detected envelop, and then restores the degraded envelop with the proposed digital filtering method. Finally the restored envelop is manipulated to the TDD synchronization signal. Our focus on the proposed algorithm is to develop it with simple feature and low cost but robust performance. The proposed scheme was implemented to the integrated system which has both RF and digital circuit and tested under the same condition with the commercial WiBro service.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.