• 제목/요약/키워드: Design Verification

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자율주행자동차의 안전 및 보안을 위한 설계 및 검증 표준: ISO/TR 4804 (Design and Verification Standard for Safety and Cybersecurity of Autonomous Cars: ISO/TR 4804)

  • 이성수
    • 전기전자학회논문지
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    • 제25권3호
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    • pp.571-577
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    • 2021
  • 본 논문에서는 자율주행자동차의 안전성 및 보안성을 보장하기 위해서 설계하고 검증하는 방법을 규정한 국제 표준인 ISO/TR 4804에 대해 다룬다. ISO/TR 4804는 자율주행자동차가 (1) 인간 운전자보다 훨씬 더 안전하고 (2) 타당하지 않은 위험이 없도록 하는 것을 목표로 하며, 이를 위해 12개의 안전성 및 보안성 원칙을 제시한다. 설계 과정에서는 (1) 안전성 및 보안성 원칙을 달성하는데 필요한 13개의 역량, (2) 이 역량을 수행하기 위해 필요한 하드웨어 및 소프트웨어 요소, (3) 이 요소를 결합한 논리적, 일반적인 아키텍쳐 등을 규정한다. 검증 과정에서는 (1) 안전성 및 보안성을 검증하기 위한 5개의 과업, (2) 이 과업을 완수하기 위한 테스트 목표, 플랫폼, 솔루션, (3) 시뮬레이션 방법 및 필드 운영 방법, (4) 하드웨어 및 소프트웨어 요소의 검증 방법 등을 규정한다. 특히 심층 신경망을 하나의 소프트웨어 요소로 간주하고, 심층 신경망이 적용된 자율주행자동차를 설계하고 검증하는 방법을 규정한다.

무인항공기용 비행자료 기록장치 소프트웨어 설계 및 검증 방안 (Software Design and Verification Method of Flight Data Recorder for Unmanned Aerial Vehicle)

  • 양서희
    • 한국항행학회논문지
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    • 제24권3호
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    • pp.163-172
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    • 2020
  • 무인항공기 사고 발생 시 사후 조사를 위한 비행자료 기록장치는 항공기 추락에 따른 극한환경에 노출된 후 비행자료를 정상 복원할 수 있도록 EUROCAE(European Organization for Civil Aviation Equipment)의 ED-112 규격을 준수하여야 한다. ED-112 규격은 유인항공기를 포함한 모든 항공기의 일반적인 요구사항을 규정하고 있기 때문에 특정 플랫폼의 형상 및 운용개념에 따라 적합한 설계 요구사항을 선택적으로 적용하여야 하므로 소프트웨어에 대한 세부 요구사항 분석이 필수적이다. 본 논문에서는 무인항공기에 적합한 소프트웨어 요구사항을 분석하고 이를 고려한 비행자료 기록장치 소프트웨어의 설계 방안을 제안한다. 또한 구현된 소프트웨어가 모든 요구사항을 고려하여 설계되었는지 확인하기 위한 각 요구사항에 대한 소프트웨어 검증 방안을 제시한다.

멀티죤 시뮬레이션을 이용한 생물안전 3등급(BSL3)시설의 설계 검증에 관한 연구 (A Study on Verification for the Design of Bio Safety Level 3 Laboratory by using Multi-zone Simulation)

  • 이현우;최상곤;홍진관
    • 대한설비공학회:학술대회논문집
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    • 대한설비공학회 2009년도 하계학술발표대회 논문집
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    • pp.745-750
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    • 2009
  • In Korea, since the implementation of the GMO Law, the intrest of biosafety level 3(BL3) lab. is increasing. In this study, using CONTAM which is applying multizone modelling, the multizone simulation for design verification of BL3 lab. was performed. In BL3 lab., because required air change rate is greater than general estimated air-conditioning load and it is difficult to maintain room pressure difference efficiently, to maintain pressure difference between laboratory rooms is important through sealing condition of doors and proper airflow control of laboratory rooms. In this study, about BL3 lab.(M. tuberculosis research lab.), the multizone simulation for four kind of biohazard scenarios was performed in the case of unexpected spread of contaminants in the laboratory room, anteroom, corridor and inside of BSC. Multizone simulation results show that these approach methods are used as a tool for the design and verification of BL3 lab.

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멀티죤 시뮬레이션을 이용한 생물안전 3등급(BSL3)시설의 설계 검증에 관한 연구 (A Study on Verification for the Design of Bio Safety Level 3 Laboratory by using Multi-zone Simulation)

  • 이현우;최상곤;홍진관
    • 설비공학논문집
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    • 제21권12호
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    • pp.671-677
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    • 2009
  • In Korea, since the implementation of the LMO Law, the interest of biosafety level 3(BL3) lab. is increasing. In this study, using CONTAM which is applying multizone modelling, the multizone simulation for design verification of BL3 lab. is performed. In BL3 lab., because required air change rate is greater than general estimated air-conditioning load and it is difficult to maintain room pressure difference efficiently, to maintain pressure difference between laboratory rooms is important through sealing condition of doors and proper airflow control of laboratory rooms. In this study, about BL3 lab,(M. tuberculosis research lab.), the multizone simulation for four kind of biohazard scenarios is carried out in the case of unexpected spread of contaminants in the laboratory room, anteroom, corridor and inside of BSC. Multizone simulation results show that these approach methods are used as a tool for the design and verification of BL3 lab.

SOC Verification Based on WGL

  • Du, Zhen-Jun;Li, Min
    • 한국멀티미디어학회논문지
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    • 제9권12호
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    • pp.1607-1616
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    • 2006
  • The growing market of multimedia and digital signal processing requires significant data-path portions of SoCs. However, the common models for verification are not suitable for SoCs. A novel model--WGL (Weighted Generalized List) is proposed, which is based on the general-list decomposition of polynomials, with three different weights and manipulation rules introduced to effect node sharing and the canonicity. Timing parameters and operations on them are also considered. Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits. The model is proved to be a uniform and efficient model for both bit-level and word-level functions. Then Based on the WGL model, a backward-construction logic-verification approach is presented, which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than $O(n^{3.6})$ and space complexity is less than $O(n^{1.5})$) without hierarchical partitioning. Finally, a construction methodology of word-level polynomials is also presented in order to implement complex high-level verification, which combines order computation and coefficient solving, and adopts an efficient backward approach. The construction complexity is much less than the existing ones, e.g. the construction time for multipliers grows at the power of less than 1.6 in the size of the input word without increasing the maximal space required. The WGL model and the verification methods based on WGL show their theoretical and applicable significance in SoC design.

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FUNCTIONAL VERIFICATION OF A SAFETY CLASS CONTROLLER FOR NPPS USING A UVM REGISTER MODEL

  • Kim, Kyuchull
    • Nuclear Engineering and Technology
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    • 제46권3호
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    • pp.381-386
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    • 2014
  • A highly reliable safety class controller for NPPs (Nuclear Power Plants) is mandatory as even a minor malfunction can lead to disastrous consequences for people, the environment or the facility. In order to enhance the reliability of a safety class digital controller for NPPs, we employed a diversity approach, in which a PLC-type controller and a PLD-type controller are to be operated in parallel. We built and used structured testbenches based on the classes supported by UVM for functional verification of the PLD-type controller designed for NPPs. We incorporated a UVM register model into the testbenches in order to increase the controllability and the observability of the DUT(Device Under Test). With the increased testability, we could easily verify the datapaths between I/O ports and the register sets of the DUT, otherwise we had to perform black box tests for the datapaths, which is very cumbersome and time consuming. We were also able to perform constrained random verification very easily and systematically. From the study, we confirmed the various advantages of using the UVM register model in verification such as scalability, reusability and interoperability, and set some design guidelines for verification of the NPP controllers.

웹 기반의 화자확인시스템 설계에 관한 연구 (A Study on the Design of Web-based Speaker Verification System)

  • 이재희;강철호
    • 한국음향학회지
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    • 제19권4호
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    • pp.23-30
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    • 2000
  • 본 연구에서는 인터넷 웹 기반의 화자확인시스템을 설계하였다. 웹 기반의 화자확인 시스템에 적용할 화자인식기법을 선정하기 위해 문자종속 화자인식기법들(DTW, DHMM, SCHMM)의 성능 및 특징들을 컴퓨터 시뮬레이션을 통하여 비교 평가하였다. 컴퓨터 시뮬레이션 결과를 이용하여 웹 기반의 화자확인시스템에 적합한 인식성능 및 초기 학습발음수를 갖는 DHMM을 화자인식기법으로 선정하고 이를 분산처리환경에서 동작하도록 Activex, DCOM기술을 이용하여 3계층방식으로 설계하였다.

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Development of Communication Protocol Verification Tool for Vital Railway Signaling Systems

  • Hwang, Jong-Gyu;Jo, Hyun-Jeong;Lee, Jae-Ho
    • Journal of Electrical Engineering and Technology
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    • 제1권4호
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    • pp.513-519
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    • 2006
  • As a very important part in development of the protocol, verifications for developed protocol specification are complementary techniques that are used to increase the level of confidence in the system functions by their specifications. Using the informal method for specifying the protocol, some ambiguity may be contained therein. This indwelling ambiguity in control systems can cause the occurrence of accidents, especially in the case of safety-critical systems. To clear the vagueness contained in the designed protocol, we use the LTS (Labeled Transition System) model to design the protocol for railway signaling. And then, we verify the safety and the liveness properties formally through the model checking method. The modal ${\mu}$-calculus, which is an expressive method of temporal logic, has been applied to the model checking method. We verify the safety and liveness properties of Korean standard protocol for railway signaling systems. To perform automatic verification of the safety and liveness properties of the designed protocol, a communication verification tool is implemented. The developed tools are implemented by C++ language under Windows XP. It is expected to increase the safety and reliability of communication protocol for signaling systems by using the developed communication verification tool.

SVM-Based Speaker Verification System for Match-on-Card and Its Hardware Implementation

  • Choi, Woo-Yong;Ahn, Do-Sung;Pan, Sung-Bum;Chung, Kyo-Il;Chung, Yong-Wha;Chung, Sang-Hwa
    • ETRI Journal
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    • 제28권3호
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    • pp.320-328
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    • 2006
  • Using biometrics to verify a person's identity has several advantages over the present practice of personal identification numbers (PINs) and passwords. To gain maximum security in a verification system using biometrics, the computation of the verification as well as the storing of the biometric pattern has to take place in a smart card. However, there is an open issue of integrating biometrics into a smart card because of its limited resources (processing power and memory space). In this paper, we propose a speaker verification algorithm using a support vector machine (SVM) with a very few features, and implemented it on a 32-bit smart card. The proposed algorithm can reduce the required memory space by a factor of more than 100 and can be executed in real-time. Also, we propose a hardware design for the algorithm on a field-programmable gate array (FPGA)-based platform. Based on the experimental results, our SVM solution can provide superior performance over typical speaker verification solutions. Furthermore, our FPGA-based solution can achieve a speed-up of 50 times over a software-based solution.

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요구조건 기준의 개발 수행을 위한 우주발사체 개발사업의 실제적인 요구조건-검증 관리 체계 (Practical Requirements and Verification Management for Requirements-based Development Process in Space Launch Vehicle Development Project)

  • 조동현;장준혁;유일상
    • 시스템엔지니어링학술지
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    • 제19권1호
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    • pp.56-63
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    • 2023
  • For the success of system development, it is necessary to systematically manage the requirements that are the basis of system development and its verification results. In order to follow the principles of SE(Systems Engineering)-based V&V(Verification&Validation) process, requirements can be managed by securing the requirements and their establishments, design compliances, and verification compliances according to the system development lifecycle. Especially, in a large-complex system research and development project, such as a space launch vehicle development project, many participants establish, verify, and validate numerous requirements together during the project. Therefore, logical and systematic requirements management, including guarantee of data integrity, change history, and traceability, is very important for multiple participants to utilize numerous requirements together without errors. This paper introduces the practical requirements and verification management for the requirements-based development process in the space launch vehicle development project.