• Title/Summary/Keyword: Design Point

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Design and Implementation of Real-time three dimensional Tracking system of gazing point (삼차원 응시 위치의 실 시간 추적 시스템 구현)

  • 김재한
    • Proceedings of the IEEK Conference
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    • 2003.07c
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    • pp.2605-2608
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    • 2003
  • This paper presents design and implementation methods of the real-time three dimensional tracking system of the gazing point. The proposed method is based on three dimensional data processing of eye images in the 3D world coordinates. The system hardware consists of two conventional CCD cameras for acquisition of stereoscopic image and computer for processing. And in this paper, the advantages of the proposed algorithm and test results ate described.

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Compensation of Discrete-Time Saturating Systems Trough Equilibrium Point Matching Method (평형점 근접 방법을 통한 이산 포화 시스템의 보상)

  • 박종구;최종호
    • 제어로봇시스템학회:학술대회논문집
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    • 1993.10a
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    • pp.189-194
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    • 1993
  • This paper presents an ARW(Anti-Reset Windup) method for discrete-time control systems with saturation nonlinearites. The method is motivated by the concept of the equilibrium point. The design parameters of the ARW scheme is explicitly derived by minimizing a reasonable performance index. The proposed method is closely related with the singular perturbed theory. The proposed method is applicable to any open-loop stable plants with saturation nonlinearities whose controllers are determined a priori by some design technique.

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Development of a Floating Point Co-Processor for ARM Processor (ARM 프로세서용 부동 소수점 보조 프로세서 개발)

  • 김태민;신명철;박인철
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.232-235
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    • 1999
  • In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.

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CAE Solid Element Mesh Generation from 3D Laser Scanned Surface Point Coordinates

  • Jarng S.S.;Yang H.J.;Lee J.H.
    • Korean Journal of Computational Design and Engineering
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    • v.10 no.3
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    • pp.162-167
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    • 2005
  • A 3D solid element mesh generation algorithm was newly developed. 3D surface points of global rectangular coordinates were supplied by a 3D laser scanner. The algorithm is strait forward and simple but it generates hexahedral solid elements. Then, the surface rectangular elements were generated from the solid elements. The key of the algorithm is elimination of unnecessary elements and 3D boundary surface fitting using given 3D surface point data.

Optimal Design of a Covering Network

  • Myung, Young-Soo
    • Journal of the Korean Operations Research and Management Science Society
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    • v.19 no.1
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    • pp.189-199
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    • 1994
  • This paper considers the covering network design problem (CNDP). In the CNDP, an undirected graph is given where nodes correspond to potential facility sites and arcs to potential links connecting facilities. The objective of the CNDP is to identify the least cost connected subgraph whose nodes cover the given demand points. The problem difines a demand point to be covered if some node in the selected graph is present within an appropriate distance from the demand point. We present an integer programming formulation for the problem and develop a dual-based solution procedure. The computational results for randomly generated test problems are also shown.

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Design-for-Testability of The Floating-Point DSP Processor (부동 소수점 DSP 프로세서의 테스트 용이 설계)

  • Yun, Dae-Han;Song, Oh-Young;Chang, Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.5B
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    • pp.685-691
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    • 2001
  • 본 논문은 4단계 파이프 라인과 VLIW (Very Long Instruction Word) 구조를 갖는 FLOVA라는 DSP 프로세서의 테스트용이 설계 기법을 다룬다. Full-scan design, BIST(Built-In-Self-Test), IEEE 1149.1의 기법들이 플립플롭과 floaing point unit, 내장된 메모리, I/O cell 등에 각각 적용되었다. 이러한 기법들은 테스트 용이도의 관점에서 FLOVA의 구조에 적절하게 적용되었다. 본 논문에서는 이와 같이 FLOVA에 적용된 테스트 용이 설계의 특징들을 중심으로 상세하게 기술한다.

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Design and MPW Implementation of 3D Graphics Floating Point Ips (3차원 그래픽용 부동 소수점 연산기 IP 설계 및 MPW 구현)

  • Lee, Jung-Woo;Kim, Ki-Chul
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.987-988
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    • 2006
  • This paper presents a design and MPW implementation of 3D Graphics Floating Point IPs. Designed IPs include adder, subtractor, multiplier, divider, and reciprocal unit. The IPs have pipelined structures. The IPs meet the accuracy required in OpenGL ES. The operation frequency of the IPs is 100MHz. The IPs can be efficiently used in 3D graphics accelerators.

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Design of a Floating Point Processor for Nonlinear Functions on an Embedded FPGA (비선형 함수 연산을 위한 FPGA 기반의 부동 소수점 프로세서의 설계)

  • Kim, Jeong-Seob;Jung, Seul
    • Proceedings of the KIEE Conference
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    • 2007.10a
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    • pp.74-76
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    • 2007
  • This paper presents the hardware design of a 32bit floating point based processor. The processor can perform nonlinear functions such as sinusoidal functions, exponential functions, and other nonlinear functions. Using the Taylor series and the Newton - Raphson method, nonlinear functions are approximated. The processor is actually embedded on an FPGA chip and tested. The numerical accuracy of the functions is compared with those computed by the MATLAB.

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A study on the Characteristics of 'Data Architecture' from the communicational point of view - Focused on WoZoCo by MVRDV - (커뮤니케이션 관점에서 살펴본 '데이터 건축'의 특성 연구 - MVRDV WoZoCo를 중심으로 -)

  • Kim, Eun-Yong;Lim, Kyung-Lan
    • Proceedings of the Korean Institute of Interior Design Conference
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    • 2005.05a
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    • pp.60-63
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    • 2005
  • After 20th century, Data tend to important in a sphere of architecture. In this study such tendency was christened a Data architecture. And The purpose of the study is to define data architecture and to find out of data architecture's merits from a communicational point of view. Above-mentioned Communication means that exchange all kinds of something between each other.

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A Study on Performance Improvement of Industrial Oil Pump Using Computational Analysis (전산해석을 이용한 산업용 오일펌프 성능개선에 관한 연구)

  • Kim, Jin-Woo;Lee, Hyun-Jun;Kong, Seok-Hwan;Lee, Seong-Won;Chung, Won-Ji
    • Journal of the Korean Society of Industry Convergence
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    • v.25 no.6_2
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    • pp.1111-1117
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    • 2022
  • Recently, interest in the circular economy has emerged in the industry. As a result, interest in Re-manufacturing, which makes old equipment similar to new products, is growing. In the machine tool industry with many aging equipment, the Re-manufacturing industry is essential, and among them, research on the performance improvement of gear type oil pumps was conducted. The purpose was to achieve the target performance of flow rate and volume efficiency by changing the shape of the gear pump housing clearance and inlet/outlet, and Computational Fluid Analysis and Central Composite Design were conducted using ANSYS CFX 2022 R2 and MINITAB®. The level of each determined factor was determined. 20 design points were derived, and the Flow Rate at each design point was calculated, and the Theoretical Flow Rate was calculated to obtain Volumetric Efficiency. The optimal design point was obtained when the Flow Rate was 140 lpm and the Volumetric Efficiency was maximum, the optimal design point was obtained when both were maximum, and the Surface Plot for each factor was obtained to identify the tendency.