• The KIPS Transactions:PartA
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• v.15A no.3
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• pp.135-140
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• 2008

This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC $0.18{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.839-844
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• 2003

For mass and volume reduction, input demultiplxer and output multiplexer of satellite transponder widely adopt dual-mode waveguide filters fer channel filters. Generally, channel filters of the input demultiplexer are doubly terminated and channel filters of manifold output multiplexer should be singly terminated fur correct operation. This paper gives a tuning method using short-ended dummy cavity for dual-mode cavity filters. Tuning is based on the match of the computed and measured phase response of reflection coefficient. This proposed method is applied to 4-pole dual-mode doubly terminated elliptic response filter and 6-pole dual-mode singly terminated elliptic response filter for demonstration of this new tuning method. It is shown that this method shows good agreement between the experimental and computed results.