• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.141-150
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• 2006

본 논문에서는 기존에 제안된 가상음향공간 모델에서 문제점으로 대두된 음향특성을 개선한 새로운 모델을 제안하였다. 제안된 가상음향효과기는 초기 잔향을 위하여 teped delay line을 사용하여 초기반사음 재현에 충실하도록 하였고, 후기 잔향을 위하여 nesed allpass delay line을 이용하여 잔향 밀도를 높이도록 고안되었다. 각 delay line의 지연 시간을 조절하여 가장 좋은 잔향 효과를 갖도록 계수 값들을 추출하였으며, 제안한 알고리즘을 일반 범용 DSP를 이용하여 구현하였으며, 실험 고찰을 통하여 기존에 제시된 모델에서의 임펄스성음에 대한 비선형적인 거친 응답과 frequency 영역에서 고르고 평탄한 잔향 밀도가 개선되어 보다 더 좋은 효과를 보임을 확인하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.156-164
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• 2014

In a delay line type of a time-to-digital converter implemented in Field Programmable Gate Array, the timing accuracy decreases for a longer carry chain. In this paper, we propose a structure that has a multi-phase clock and a state machine to check metastability; this would reduce the required length of the carry chain with the same time resolution. To reduce the errors caused by the time difference in the four delay lines associated with a four-phase clock, the proposed TDC generates a single input pulse from four phase clocks and uses a single delay line. Moreover, the state machine is designed to find the phase clock that is used to generate the single input pulse and determine the metastable state without a synchronizer. With the measurement range of 1 ms, the measured resolution was 22 ps, and the non-linearity was 25 ps.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.2
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• pp.231-245
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• 1996

Semiconductor manufacturing line includes several batch processes which are to be controlled effectively to enhance the productivity of the line. The key problem in batch processes is a dynamic batch sizing problem which determines number of lots processed simultaneously in a single botch. The batch sizing problem in semiconductor manufacturing has to consider delay of lots, setup cost of the process, machine utilization and so on. However, an optimal solution cannot be attainable due to dynamic arrival pattern of lots, and difficulties in forecasting future arrival times of lots of the process. This paper proposes an efficient batch sizing heuristic, which considers delay cost, setup cost, and effect of the forecast errors in determining the botch size dynamically. Extensive numerical experiments through simulation are carried out to investigate the effectiveness of the proposed heuristic in four key performance criteria: average delay, variance of delay, overage lot size and total cost. The results show that the proposed heuristic works effectively and efficiently.

• Korean Journal of Optics and Photonics
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• v.17 no.2
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• pp.159-164
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• 2006

We demonstrate a compact optical coherence tomography(OCT) system based on the optical fiber delay line controlled by a cylindrical piezo-electric transducer(PZT). An 18-m length of single mode fiber is wrapped under constant tension around a PZT. Approximately 134 windings are used. Wraps of the long length of fiber allow the small expansion of the PZT to be magnified to an optical path length delay of 0.78 m. The OCT system shows characteristics for 2-dimensional imaging, exhibiting 96.9dB of signal-to-noise ratio(SNR), $18.6{\pm}0.5\;{\mu}m$ of axial resolution, and $5\;{\mu}m$ of lateral resolution with samples.

• Current Optics and Photonics
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• v.3 no.1
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• pp.16-21
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• 2019

We present a broad-bandwidth comb-spacing-swept source (CSWS) based on a differential polarization delay line (DPDL) for interferometric three-dimensional (3D) imaging. The comb spacing of the CSWS is repeatedly swept by the tunable DPDL in the multiwavelength source to provide depth-scanning optical coherence tomography (OCT). As the polarization differential delay of the DPDL is tuned from 5 to 15 ps, the comb spacing along the wavelength continuously varies from 1.6 to 0.53 nm, respectively. The wavelength range of various semiconductor optical amplifiers and the cavity feedback ratio of the tunable fiber coupler are experimentally selected to obtain optimal conditions for a broader 3-dB bandwidth of the multiwavelength spectrum and thus provide a higher axial resolution of $35{\mu}m$ in interferometric OCT imaging. The proposed CSWS-OCT has a simple imaging interferometer configuration without reference-path scanning and a simple imaging process without the complex Fourier transform. 3D surface images of a via-hole structure on a printed circuit board and the top surface of a coin were acquired.

• Korean Journal of Optics and Photonics
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• v.18 no.2
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• pp.162-166
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• 2007

In this paper, we propose a WDM optical true time-delay (OTTD) beam former for phased way antenna (PAA) systems. It is composed of a delay lines matrix and a multiwavelength source with discrete DFB laser diodes. The building block of a delay lines matrix is a $2\times2$ optical MEMS switch with proper fiber-optic delay line connected between cross ports. A $4\times3$ matrix using four DFB lasers has been fabricated with unit time-delay difference of 12 ps. Maximum time-delay error was measured to be -1.74 ps and +1.14 ps at a radiation angle of $46.05^{\circ}$, corresponding to error range of $-2.87^{\circ}\sim+1.88^{\circ}$. By measuring time-delays at six different RF frequencies from 5- to 10-GHz, we verified the true time-delay characteristic of our OTTD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10B
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• pp.1240-1245
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• 2011

In this paper, channel modeling and analysis of wireless visible light communication(VLC) were studied in indoor circumstance. Photons emitted from LED straightly moved and navigated within indoor, after that a part of photons reached on PD via LOS(Line Of Sight) or NLOS(None Line Of Sight). These received signals had characteristics of delay profile and attenuation, which was multiple-path fading. In this paper, computer simulation of VLC channel was executed under the condition that two LEDs were used for transmitter and three PDs were located at different positions of the 20*8*2.3m sized indoor. BER performance simulation was excuted based on the characteristics of each VLC channel.