• Journal of Power System Engineering
• /
• v.13 no.2
• /
• pp.71-82
• /
• 2009

This paper presents a real-time haptic rendering method for a realistic force feedback in a remote environment with varying communication time-delay. The remote environment is assumed as a virtual environment based on a computer graphics, for example, on-line shopping mall, internet game and cyber-education. The properties of a virtual object such as stiffness and viscosity are assumed to be unknown because they are changed according to the contact position and/or a penetrated depth into the object. The DARMAX model based output estimator is proposed to trace the correct impedance of the virtual object in real-time. The output estimator is developed on the input-output relationship. It can trace the varying impedance in real-time by virtue of P-matrix resetting algorithm. And the estimator can trace the correct impedance by using a white noise that prevents the biased input-output information. Realistic output forces are generated in real-time, by using the inputs and the estimated impedance, even though the communication time delay and the impedance of the virtual object are unknown and changed. The generated forces trace the analytical forces computed from the virtual model of the remote environment. Performance is demonstrated by experiments with a 1-dof haptic device and a spring-damper-based virtual model.

• Journal of electromagnetic engineering and science
• /
• v.18 no.1
• /
• pp.20-28
• /
• 2018

The time synchronization of each sub-unit of a pulsed generator is important to generate an output high-power radio frequency (RF) signal. To obtain the time synchronization between an input RF signal fed by an external source and an electron beam produced by an electric pulse generator, the influence of different charging voltages on a delay and a rise time of the output pulse waveform in the electric pulse generator should be carefully considered. This paper aims to study the timing characteristics of the delay and the rise time as a function of different charging voltages with a peak value of less than -35 kV in the high-voltage pulse generator, including a trigger generator (TG) and a pulse-forming line (PFL). The simulation has been carried out to estimate characteristics in the time domain, in addition to their output high-voltage amplitude. Experimental results compared with those obtained by simulation indicate that the delay of the output pulses of the TG and PFL, which are made by controlling the external triggering signal with respect to different charging voltages, is getting longer as the charging voltage is increasing, and their rise times are inversely proportional to the amplitude of the charging voltage.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.2 no.1
• /
• pp.30-36
• /
• 1992

In order to measure the characteristics of Surface Acousitc Wave(SA W) with compositions of $LiNbO_3$ single crystal, $128^{\circ}$ Y cut wafer was fabricated from $LiNbO_3$ single crystals with the composition range of 47-50 $Li_2O$mol%. Delay lines were formed on the $128^{\circ}$ Y cut wafer using photolithography technique. Delay time was measured by pulse-echo overlap method. The compositional dependence of SAW characteristics, SAW velocity, electro-mechanical coupling coefficient$(K_s^2)$ and temperature coefficient of delay time(TCD), were investigated.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.38 no.10
• /
• pp.24-33
• /
• 2001

Delay, delay variation and packet loss rate are principal QoS(Quality of Service) elements of packet communication. This paper proposes a new buffer allocation mechanism to improve the packet loss performance in such a situation that multiple logical buffers share a single physical memory buffer. In the proposed buffer allocation mechanism, the movement of dynamic threshold follows a curved track instead of a straight line which is used in the DT(dynamic threshold) mechanism. In order evaluate the effectiveness of the proposed mechanism, it is compared with the existing previously proposed mechanisms in several aspects including NC(no control), ST(Static Threshold) and DT mechanisms.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.10
• /
• pp.105-113
• /
• 2004

This paper presents a design method for an asynchronous memory with a completion signal generation circuit meeting D-I model. The proposed design method is to generates a completion signal with dummy cell and a completion signal generation circuit to indicate completion of the required read or write operation to the processor. Dividing a memory exponentially to consider delay of a bit-line and a memory cell makes memory operates as a D-I model with minimum addition of redundant circuit. The proposed memory partitioning algorithm that divides entire memory into the several partitions with a exponentially increased size reduces the memory access delay by 40% compared with a conventional partitioning method to the same size.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.2
• /
• pp.73-79
• /
• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Journal of IKEEE
• /
• v.14 no.3
• /
• pp.232-235
• /
• 2010

A 60GHz active phase shifter with 65nm CMOS is presented by replacing passive switches in switched-line type phase shifter with active ones. Active-switch phase shifter is composed of active-switch blocks and passive delay network blocks. The active-switch phase shifter design is compact compare with the conventional vector-sum phase shifter. Active-switch blocks are designed to accomplish required input and output impedances whose requirements are different whether the switch is on or off. And passive delay network blocks are composed of lumped L,C instead of normal microstrip line to reduce the size of the circuit. An 1-bit phase shifter is fabricated by TSMC 65nm CMOS technology and measurement results present -4dB average insertion loss and 120 degree phase shift at 65GHz.

• Journal of Internet Computing and Services
• /
• v.12 no.5
• /
• pp.11-19
• /
• 2011

In this paper, Service Boundary Line approximation method is proposed to improve the accuracy of aggregated link state information for source routing in transport networks that conduct hierarchical QoS routing. The proposed method is especially useful for aggregating links that have both delay and bandwidth as their QoS parameters. This method selects the main path weight in the network and transports the data to the external networks together with the aggregation information, reducing information distortion caused from the loss of some path weight during aggregation process. In this paper, the main path weight is defined as outlier. Service Boundary Line has 2k+5parameters. k is the number of outliers. The number of storage spaces of Service Boundary Line changes according to the number of outliers. Simulation results show that our approximation method requires a storage space that 1.5-2 times larger than those in other known techniques depending on outlier selection method, but its information accuracy of proposed method in the ratio between storage space and information accuracy is higher.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.10
• /
• pp.2209-2216
• /
• 2011

In this paper, we design a 32-bit eFuse OTP memory for PMICs using MagnaChip's $0.18{\mu}m$ process. We solve a problem of an electrical shortage between an eFuse link and the VSS of a p-substrate in programming by placing an n-well under the eFuse link. Also, we propose a WL driver circuit which activates the RWL (read word-line) or WWL (write word-line) of a dual-port eFuse OTP memory cell selectively when a decoded WERP (WL enable for read or program) signal is inputted to the eFuse OTP memory directly. Furthermore, we reduce the layout area of the control circuit by removing a delay chain in the BL precharging circuit. We'can obtain an yield of 100% at a program voltage of 5.5V on 94 manufactured sample dies when measured with memory tester equipment.

• Journal of The Korean Astronomical Society
• /
• v.28 no.2
• /
• pp.245-253
• /
• 1995

We have analyzed the time series of Ca II H,K and ${\lambda}8498$ line profiles taken for a sunspot (SPO 5007) with the Echelle spectrograph attached to Vacuum Tower Telescope at Sacramento Peak Solar Observatory. Each set of spectra was taken simultaneously for 20 minutes at a time interval of 30 seconds. A total of 40 photographic films for each line was scanned by a PDS at Korea Astronomy Observatory. The central peak intensity of Ca II H ($I_{max}$), the intensity measured at ${\Delta}{\lambda}=-0.1{\AA}$ from the line center of ${\lambda}8498(I_{{\lambda}8489})$, the radial velocity ($V_r$) and the Doppler width (${\Delta}{\lambda}_D$) estimated from Ca II H have been measured to study the dynamical behaviors of the sunspot chromosphere. Fourier analysis has been carried out for these measured quantities. Our main results are as follows: (1) We have confirmed the 3-minute oscillation being dominant throughout the umbra. The period of oscillations jumps from 180 sec in the umbra to 500 to 1000 sec in the penumbra. (2) The nonlinear character of the umbral oscillation is noted from the observed sawtooth shaped radial velocity fluctuations with amplitudes reaching up to $5{\sim}6\;km/sec$. (3) The spatial distribution of the maximum powers shows that the power of oscillations is stronger in the umbra than in the penumbra. (4) The spatial distributions of the time averaged < $I_{max}$ > and < $V_r$ > across the spot are found to be nearly axially symmetric, implying that the physical quantities derived from the line profiles of Ca II H and ${\lambda}8498$ are inherently associated with the geometry of the magnetic field distribution of the spot. (5) The central peaks of the CaII H emission core lead the upward motions of the umbral atmosphere by $90^{\circ}$, while no phase delay is found in intensities between $I_{max}$ and $I_{{\lambda}8498}$, suggesting that the umbral oscillation is of standing waves.