• Explosives and Blasting
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• v.21 no.1
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• pp.69-76
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• 2003

Test blasting has been performed with V-cut to investigate the characteristics. Blasting vibrations were measured at two directions, the proceed direction and side direction. Propagation characteristics were determined by regression analysis; square root scaled distance and cube root scaled distance with maximum charge per delay of the blast. Testing result, The cross point was 62m in the allowable vibration velocity of 3mm/sec and 46m In 5mm/sec. Also, vibration level with measuring point was highest and decayed fastest, adapting to cube root scaled distance, for the proceed direction on ground.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.72-79
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• 2003

This paper proposes a 32${\times}$32 Modified Booth multiplier using CMOS multiple-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 67.1% and 37.3%, compared with that of the voltage mode binary multiplier and the previous multiple-valued logic multiplier, respectively. The multiplier is designed with a 0.35${\mu}{\textrm}{m}$ standard CMOS technology at a 3.3V supply voltage and unit current 10$mutextrm{A}$, and verified by HSPICE. The multiplier has 5.9㎱ of propagation delay time and 16.9mW of power dissipation. The performance is comparable to that of the fastest binary multiplier reported.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.26 no.1
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• pp.1-11
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• 2002

Flow of fluid has been studied in various fields of fluid engineering. To hydraulic engineers, the unsteady flow such as pulsation and liquid hammering in pipes has been considered as a serious trouble. So we are supposed to approach the formalized mathematical model by using more exact momentum equation for fluid transmission lines. Most of recent studies fur pipe line have been studied without considerations of variation of viscosity and temperature, which are the main factors of pressure loss causing the friction of fluid inside pipe line. Frequency response experiments are carried out with use of a rotary sinusoidal flow generator to investigate wave equation take into account viscosity and temperature. But we observed that measured value of gains are reduced as temperature increased. And it was respectively observed that the measured value of gains are reduced and line width of gain is broadened out, when temperature was high in the same condition. As we confessed, pressure loss and phase delay are closely related with the length, diameter and temperature of pipe line. In addition, they are the most important factors, when we decide the momentum energy of working fluid.

• Proceedings of the KSME Conference
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• 2000.04b
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• pp.447-452
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• 2000

The low-emission and high-performance diesel combustion is an important issue in the combustion research community. In order to understand the detailed diesel flame field involving the complex Physical Processes, It Is quite desirable to study diesel spray dynamics, auto-ignition and spray flame propagation. Dynamics of fuel spray is a crucial element for air-fuel mixture formation flame stabilization and pollutant formation. In the present study, the diesel RCM (Rapid Compression Machine) and the Electric Control injection system have been designed and developed to investigate the effects of injection Pressure, injection timing, and intake air temperature on spray dynamics and diesel combustion processes. In terms of the macroscopic spray combustion characteristics it is observed that the fuel jet atomization and the droplet breakup processes become much faster by increasing the injection pressure and the spray angle. With increasing the cylinder pressure there is a tendency that the shape of spray pattern in the downstream region tends to be spherical due to the increase of air density and the corresponding drag force. Effects of intake temperature and injection pressure on auto-ignition is experimently analysed and discussed in detail.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.12
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• pp.1484-1493
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• 1992

In this paper, we propose the polarization coding of optical logic gates using filters and LCTV's, and represent the real-time system of an optical parallel adder to improve a carry propagation delay time. We fabricated a polarization filter for the polarization coding of a cell and an electrical system instead of an optical flip-flop which was necessary to an optical parallel adder. We used an optical fiber to play a part of decoding mask and interconnections in an optical parallel adder. The experimental results show that the polarization coding of a cell can represent 16 optical logic functions and that the implemented optical parallel adder can operate in real-time.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.8
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• pp.442-450
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• 2000

Active noise control is an approach to noise reduction in which a secondary noise source that destructively interferes with the unwanted noise. In general, active noise control systems rely on multiple sensors to measure the unwanted noise field and the effect of the cancellation. This paper develops an approach that utilizes a single sensor. The noise field is modeled as a stochastic process, and a time-adaptive algorithm is used to adaptively estimate the parameters of the process. Based on these parameter estimates, a canceling signal is generated. Opppenheim model assumed that transfer function characteristics from the canceling source to the error sensor is only propagation delay. But this paper proposes a modified Oppenheim model by considering transfer characteristics of acoustic device and noise path. This transfer characteristics is adaptively cancelled by adaptive model. This is proved by computer simulation with artifically generated random noise and sine wave noise. The details of the proposed architecture, and theoretical simulation and experimental results of the noise cancellation system for three dimension enclosure are presented in the paper.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.97-102
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• 2001

In computer-aided design, partitioning is task of clustering objects into groups to that a given objection function is optimized It is used at the layout level to fin strongly connected components that can be placed together in order to minimize the layout area and propagation delay. Partitioning can also be used to cluster variables and operation into groups for scheduling and unit selection in high-level synthesis. The most popular algorithms partitioning include the Kernighan-Lin algorithm Fiduccia-Mattheyses heuristic and simulated annealing In this paper we propose a genetic algorithm searching solution space for the circuit partitioning problem. and then compare it with simulated annealing by analyzing the results of implementation.

• Nuclear Engineering and Technology
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• v.33 no.1
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• pp.1-11
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• 2001

In contrast with conventional fieldbus researches which are focused merely on real-time performance, this study aims to evaluate the real-time performance of the communication system including fault-tolerant mechanisms Maintaining performance in presence of recoverable faults is very important in case that the communication network is applied to a highly reliable system such as next generation Nuclear. Power. Plant (NPP). If the tie characteristics meet the requirements of the system, the faults will be recovered by fieldbus recovery mechanisms and the system will be safe. If the time characteristics can not meet the requirements, the faults in the fieldbus can propagate to the system failure. In this study, for the purpose of investigating the time characteristics of fieldbus, the recoverable faults are classified and then the formulas that represent delays including recovery mechanisms are developed. In order to validate the proposed approach, we have developed a simulation model that represents the Korea Next Generation Reactor (KNGR) NSSS Process Control System (NPCS). The results of the simulation show us the reasonable delay characteristics of the fault cases with recovery mechanisms. Using the simulation results and the system requirements, we also can calculate the failure propagation probability from fieldbus to outer system.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.1
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• pp.9-14
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• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.8
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• pp.742-747
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• 2015

The quality of steel plate products is determined by the number of defects and the process problems are estimated by shapes of defects. Therefore pinholes defects of cold rolled steel have to be controlled. In order to improve productivity and quality of products, within each production process, the product is inspected by an adequate inspection system individually in the lines of steelworks. Among a number of inspection systems, we focus on the pinholes detection system. In this paper, we propose an embedded system using FPGA which can detect pinholes defects. The proposed system is smaller and more flexible than a traditional system based on expensive frame grabbers and PC. In order to detect consecutive defects, FPGAs acquire two dimensional image and process the image in real time by using correlation of lines. The proposed pinholes detection algorithm decreases arithmetic operations of image processing and also we designed the hardware to shorten the data path between logics due to decreasing propagation delay. The experimental results show that the proposed embedded system detects the reliable number of pinholes in real time.