• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.829-832
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• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국제학술편); Seoul National University, Seoul; 20-22 Oct. 1993
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• pp.1-6
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• 1993

This report proposes a novel method of identification of continuous time-delay systems from sampled input-output data. By the aid of a digital pre-filter, an approximated discrete-time estimation model is first derived, in which the system parameters remain in their original form and the time delay need not be an integral multiple of th sampling period. Then an identification method combining the common linear least squares(LS) method or the instrumental variable(IV) method with the genetic algorithm(GA) is proposed. That is, the time-delay is selected by the GA, and the system parameters are estimated by the LS or IV method. Furthermore, the proposed method is extended to the case of multi-input multi-output systems where the time-delays in the individual input channels may differ each other. Simulation resutls show that our method yields consistent estimates even in the presence of high measurement noises.

• 제어로봇시스템학회논문지
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• 제9권3호
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• pp.196-203
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• 2003

Recent increase in accessibility to the internet makes it easy to use the internet-connected devices. The internet could allow any user can reach and command any device that is connected to the network. But these teleoperation systems using the internet connected device have several problems such as the network time delay, data loss and development cost of an application for the communication with each other. One feasible solution is to use local and external network line for the network time delay, transmission control protocol for data loss and Java language to reduce the development period and cost. In this study, web-based remote control system using Java language is newly proposed and implemented to a pneumatic servo control system to solve the time delay, data loss and development cost. We have conducted several experiments using pneumatic rodless cylinder through the internet and verified that the proposed remote control system was very effective.

• 한국멀티미디어학회논문지
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• 제20권2호
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• pp.254-260
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• 2017

Data packets from sensor nodes scattered over measuring fields are generally forwarding to the sink node, which may be connected to the wired networks, in a wireless sensor network. So many data packets are gathered near the sink node, resulting in significant data packet collisions and severe transmission latency. In an event detection application such as object tracking and military, bursty data is generated when an event occurs. So many data packet should be transmitted in a limited time to the sink node. In this paper, we present a delay efficient and bursty traffic friendly MAC protocol called DEBF-MAC protocol for wireless sensor networks. The DEBF-MAC uses a slot-reserved mechanism and sleep period control method to send multiple data packets efficiently in an operational cycle time. Our simulation results show that DEBF-MAC outperforms DW-MAC and SR-MAC in terms of energy consumption and transmission delay.

• ETRI Journal
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• 제39권4호
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• 한국식품영양학회지
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• 제31권5호
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• pp.577-586
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• 2018

The proximate compositions, quality and physicochemical characteristics of mung-bean cultivars cultivated in the north-central region of South Korea with different seeding periods were evaluated. A significant difference was noted in the proximate compositions and chromaticity of mung-beans according to cultivars and different seeding periods. Crude ash and protein content decreased with the delay in seeding period and a slight increase in carbohydrate content was observed. Redness of the other five cultivars increased with the delay in seeding period except for the cultivar Jangan, while the yellowness decreased in cultivars Geumsung and Jangan. Water binding capacity of the $1^{st}$, $2^{nd}$ and $3^{rd}$ seeding on the cultivar Eoul was 115.15, 99.76 and 96.31%, respectively, and a decrease in the binding capacity was observed with the delay in seeding periods. Water solubility index and swelling power were significantly different among cultivars. Total polyphenol content of $1^{st}$ and $2^{nd}$ seeding on the cultivar Jangan was 8.59 and 8.57 mg GAE/g, respectively, and a decrease was observed with the delay in seeding periods except for the cultivar Sohyeon. Total flavonoid content of $1^{st}$ seeding on the cultivar Jangan was 5.25 mg CE/g, which decreased with the delay in seeding periods. DPPH radical scavenging activity of $1^{st}$ seeding on the cultivars Geumsung and Kyungseon was 2.44 and 2.32 mg TE/g, respectively, which decreased with the delay in seeding periods. The BTS radical scavenging activity of $1^{st}$ seeding on the cultivar Jangan was 6.98 mg TE/g. In the present study, the variations in phenol content and radical scavenging activity were observed to be dependent on the cultivars and seeding periods.

• 전자공학회논문지SC
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• 제37권3호
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• pp.44-54
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• 2000

본 논문에서는 표준 메모리 공정에 구현 가능한 주파수 적응성을 갖는 부지연 회로의 설계기법에 대해 제안한다. 제안하는 설계기법은 기본적으로 아날로그 SMD (synchronous mirror delay) 형태의 부지연 회로로서 입력클록의 주기와 구현하고자 하는 부의 지연 시간의 차이에 해당하는 시간을 아날로그 회로의 개념으로 측정하고 다음 번 주기에서 반복한다. 출력클록의 발생과 관련되는 부수적인 지연을 측정단의 앞 단인 지연모델 단에서 상쇄하는 기존의 SMB 기법과는 달리, 반복단에서 상쇄하는 새로운 기법을 통하여 넓은 부지연 범위를 구현하여 특히 고속동작에서의 부지연 특성을 원할하게 한다. 또한 넓은 범위의 주파수 동작범위를 구현하기 위해 해당하는 주파수 범위에서 아날로그 회로가 최적의 동작 조건을 갖추도록 하기 위한 새로운 주파수 감지기 및 최적조건 설정기법을 제안한다. 제안된 회로의 응용으로서 초고속 DRAM인 DDR SDRAM에 적용하는 예를 보였으며, 0.6㎛ n-well double-poly double-metal CMOS 공정을 사용하여 모의실험 함으로써 그 유용성을 입증한다.

• 대한전자공학회논문지TC
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• 제47권8호
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• pp.1-8
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• 2010

본 논문에서는 Cyclic prefix 형태의 보호구간을 갖는 비동기 MC-CDMA 상향 링크 시스템의 시간 옵셋의 영향을 주파수 선택적 다경로 페이딩 채널에 대하여 분석하였다. 분석을 위하여 시간 옵셋을 보호구간 및 최대 접속 지연 시간 (maximum access delay time)과 관련하여 모델링하였다. 수식적 분석을 통하여 시간 옵셋이 원하는 신호성분의 전력 누수와 자기 간섭성분을 발생시키는 것을 확인하였다. 이러한 시간 옵셋이 유효 SNR 및 평균 오류율에 미치는 영향을 분석하였다. 근사화를 통하여 평균 오류율 및 SNR 감쇄를 닫혀진 형태로 유도하였다. 분석결과의 정확성은 모의실험 결과와의 비교를 통해 다양한 시간 옵셋 및 SNR에 대해 검증하였다.

• Journal of Preventive Medicine and Public Health
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• 제53권3호
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• pp.164-167
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• 2020

Objectives: As of March 3, 2020, the Shincheonji religious group accounted for the majority of Korean cases of coronavirus disease 2019 (COVID-19). Nonetheless, the most likely cause of the broad spread of COVID-19 among members of the Shincheonji religious group remains largely unknown. Methods: We obtained data of laboratory-confirmed cases related to the Shincheonji religious group from press releases by Korean public health authorities and news reports. We measured the period from the date of illness onset to the date of COVID-19 confirmation. Results: We analysed data from 59 cases (median age, 30 years). The estimated median period between the date of symptom onset and the date of COVID-19 confirmation was 4 days (95% confidence interval, 1-12). Conclusions: There was a delay in COVID-19 confirmation from the date of illness onset among the cases linked to the Shincheonji religious group. This delay likely contributed to the occurrence of many cases of COVID-19 in the group.

• Journal of Power Electronics
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• 제4권2호
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• pp.102-111
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• 2004

This paper is concerned with a deadbeat current control implementation of shunt-type three-phase active power filter (APF). Although the one-dimensional deadbeat control method can attain time-optimal response of APF compensating current, one sampling period is actually required fur its settling time. This delay is a serious drawback for this control technique. To cancel such a delay and one more delay caused by DSP execution time, the desired APF compensating current has to be predicted two sampling periods ahead. Therefore an adaptive predictor is adopted for the purpose of both predicting the control error of two sampling periods ahead and bringing the robustness to the deadbeat current control system. By adding the adaptive predictor output as an adjustment term to the reference value of half a source voltage period before, settling time is made short in a transient state. On the other hand, in a steady state, THD (total harmonic distortion) of the utility grid side AC source current can be reduced as much as possible, compared to the case that ideal identification of controlled system could be made.