• The KIPS Transactions:PartC
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• v.11C no.3
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• pp.345-352
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• 2004

Recently, contents distribution technologies have been used to cope with the explosive demand for Web services. In this paper, we addressed the issue of the optimal placement of replicas in the environment where Web contents are replicated. We placed replicas so that clients can have access to replicas with the proper delay and bandwidth. We attempted to solve the problem via dynamic programming considering cost of delay and traffic We have come up with time complexity that is less than $O(n^2)$. We defined the threshold and proved that our algorithm guarantees the reliable services.

• Journal of the Korean Society for Aviation and Aeronautics
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• v.23 no.1
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• pp.41-48
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• 2015

Being a cost-efficient solution for alleviating the traffic congestion in airspace, Air Traffic Flow Management (ATFM) has drawn more attentions from not only air traffic controllers but also researchers in the field of Air Traffic Management (ATM). Among other ATFM initiatives, it is believed that Ground Delay Program (GDP) could be effectively applied to reduce the congestion particularly in the relatively small airspace with dense traffic demand. This paper introduces a novel way that suggests flights to be delayed on the departing airports together with amount of the delays (in time) for those flights to be delayed. Adopting a fast-time simulation for predicting airspace delay of each flight for a given flight plan, the method is designed to iteratively and incrementally adjust the departure times in the plan towards reducing total airspace delays. Applying the method to Jeju airport with a hypothetically high demand, the paper demonstrates the airspace delay could be significantly reduced by applying GDP at Gimpo airport where more than 60% of Juju-bound flights departure. Although the simulation model needs to be calibrated and validated for the real-world application, the results clearly shows that the approach can possibly implemented as a tool for preparing the daily plan at the pre-tactical stage defined in the ICAO ATFM manual.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1373-1381
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• 1999

이 논문에서는 통신망 설계 응용분야의 문제를 그래프 이론 문제로써 고려해 보았다. 개별 기업체가 서로 떨어진 두 곳을 연결하고자 할 때 공용통신망의 회선을 빌려 통신망을 구축하게 되는데 많은 경우 여러 종류의 회선들이 공급됨으로 어떤 회선을 선택하느냐의 문제가 생긴다. 일반적으로 빠른 회선(low delay)은 느린 회선(high delay)에 비해 비싸다. 그러나 서비스의 질(Quality of Service)이라는 요구사항이 종종 종단지연(end-to-end delay)시간에 의해 결정되므로, 무조건 낮은 가격의 회선만을 사용할 수는 없다. 결국 개별 기업체의 통신망을 위한 통로를 공용 통신망 위에 덮어씌워(overlaying) 구축하는 것의 여부는 두 개의 상반된 인자인 가격과 속도의 조절에 달려 있다. 따라서 일반적인 최소경로 찾기의 변형이라 할 수 있는 다음의 문제가 본 논문의 관심사이다. 두 개의 지점을 연결하는데 종단지연시간의 한계를 만족하면서 최소경비를 갖는 경로에 대한 해결을 위하여, 그래프 채색(coloring) 문제와 최단경로문제를 함께 포함하는 그래프 이론의 문제로 정형화시켜 살펴본다. 배낭문제로의 변환을 통해 이 문제는 {{{{NP-complete임을 증명하였고 {{{{O($\mid$E$\mid$D_0 )시간에 최적값을 주는 의사선형 알고리즘과O($\mid$E$\mid$)시간의 근사 알고리즘을 보였다. 특별한 경우에 대한 {{{{O($\mid$V$\mid$ + $\mid$E$\mid$)시간과 {{{{O($\mid$E$\mid$^2 + $\mid$E$\mid$$\mid$V$\mid$log$\mid$V$\mid$)시간 알고리즘을 보였으며 배낭 문제의 해결책과 유사한 그리디 휴리스틱(greedy heuristic) 알고리즘이 그물 구조(mesh) 그래프 상에서 좋은 결과를 보여주고 있음을 실험을 통해 확인해 보았다.Abstract This paper considers a graph-theoretic problem motivated by a telecommunication network optimization. When a private organization wishes to connect two sites by leasing physical lines from a public telecommunications network, it is often the cases that several categories of lines are available, at different costs. Typically a faster (low delay) lines costs more than a slower (high delay) line. However, low cost lines cannot be used exclusively because the Quality of Service (QoS) requirements often impose a bound on the end-to-end delay. Therefore, overlaying a path on the public network involves two diametrically opposing factors: cost and delay. The following variation of the standard shortest path problem is thus of interest: the shortest route between the two sites that meets a given bound on the end-to-end delay. For this problem we formulate a graph-theoretical problem that has both a shortest path component as well as coloring component. Interestingly, the problem could be formulated as a knapsack problem. We have shown that the general problem is NP-complete. The optimal polynomial-time algorithms for some special cases and one heuristic algorithm for the general problem are described.

• International conference on construction engineering and project management
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• 2011.02a
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• pp.614-620
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• 2011

Delays in completing construction projects have significant financial and social impact to all parties involved in the construction process and in particular in developing countries. This is very evident in most construction projects in Libya and in both public and private sectors. The research study was initiated by Libyan Government and the main aim of the project is to develop a new strategy in reducing the impact of delay factors. In order to achieve this, a number of objectives have been set-to conduct a comprehensive literature survey, to conduct a comparative study of the delay factors in project completion in both Libya and UK using semi structured questionnaire and finally, to identify and analyse the causes of delay and ranked them using frequency of occurrence and severity. The critical causes of delay for construction projects were quite different between Libya and UK. For the former, the most critical causes of delay in Libyan construction industry were low skills of manpower, changes in the scope of the project, slowness in giving instruction and poor qualification of consultant, while for the latter they were financial problems, bad weather conditions on the job site and change in the scope of project. Statistical experiments including Paired Samples T-Test, was run to test the significance of the survey data in both countries Libya and UK. The statistical results confirmed the collected data from the survey were significant.

• Journal of Korean Institute of Industrial Engineers
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• v.24 no.2
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• pp.241-249
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• 1998

In this paper, we seek to find an optimal allocation of link capacity in a data communication network. The architecture of the data communication network considered in the study is an online-service network based on public switched telephone network(PSTN) and packet switched data network(PSDN). In designing the architecture of the network, we need to deal with various measures of quality of service(QoS). Two important service measures are the call blocking probability in PSTN and the data transfer delay time in PSDN. Considering the tradeoff between the call blocking probability and the data transfer delay time in the network, we have developed the optimal link capacity allocation model that minimizes the total link cost, while guarantees the call blocking probability and the data transfer delay time within an acceptable level of QoS. This problem can be formulated as a non-linear integer programming model. We have solved the problem with tabu search and simulated annealing methods. In addition, we have analyzed the sensitivity of the model and provided the insight of the model along with computational results.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1639-1651
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• 1998

In this paper, we present analytical and simulation models for evaluating the operation of a uniprocessor computer which utilizes a time redundant approach (such as recomputation by shilted operands) for lault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions 01 each job must be processed. Three methods for appropriately scheduling the primary and sL'Condary versions of the jobs are proposed and analyzed. The proposed scheduling methods take into account the load and the fault rate of the uniprocessor to evaluate two figures of merit for cost and profit with respect to a delay in response time due to faults and fault tolerance. Our model utilizes a fault-tolerant schedule according to which it is possible to find an optimal delay (given by $\kappa$) based on empiric parameters such as cost, the load and the fault rate of the uniprocessor.

• 한국정보통신설비학회:학술대회논문집
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• 2009.08a
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• pp.275-280
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• 2009

Femtocells are viewed as a promising option for mobile operators to improve coverage and provide high-data-rate services in a cost-effective manner Femtocells can be used to serve indoor users, resulting in a powerful solution for ubiquitous indoor and outdoor coverage. TThe frequency accuracy and phase alignment is necessary for ensuring the quality of service (QoS) forapplications such as voice, real-time video, wireless hand-off, and data over a converged access medium at the femtocell. But, the GPS has some problem to be used at the femtocell, because it is difficult to set-up, depends on the satellite condition, and very expensive. The IEEE 1588 specification provides a low-cost means for clock synchronisation over a broadband Internet connection. The Time of Packet (ToP) specified in IEEE 1588 is able to synchronize distributed clocks with an accuracy of less than one microsecond in packet networks. However, the timing synchronization over packet switched networks is a difficult task because packet networks introduce large and highly variable packet delays. This paper proposes an enhanced filter algorithm to reduce ths packet delay variation effects and maintain ToP slave clock synchronization performance. The results are presented to demonstrate in the intra-networks and show the improved performance case when the efficient ToP filter algorithm is applied.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.577-583
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• 2011

Radar performance test is one of the major steps for radar system design. However, it is restricted by time and cost when radar performance tests are performed with opportunity targets. So various simulated target generators are developed and used to evaluate radar performance. To simulate the target's range, most of simulated target generators are developed with optical line or DRFM(Digital RF Memory) technique but there are many restrictions such as limit of range imitation and test scenario because of their original usage. In this paper, DDL(Digital Delay Line) module for development of simulated target generator is designed with precise range simulation and easily embodiment feature. And pulse recognition and delay gap detection technique are used to simulate the time delay without distortions. Developed DDL module performances are verified through their performance tests and test results are described in this paper.