• Journal of IKEEE
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• v.22 no.3
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• pp.862-865
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• 2018

The proposed scheme minimizes the Idle time under the residual energy of the sensor node to adjust the Sleep-Wakeup period and minimize unnecessary energy consumption. It is The proposed scheme minimizes the Idle time under the residual energy of the sensor node to adjust the Sleep-Wakeup period and minimize unnecessary energy consumption. It is an important process to control the Application Packet Framework including the PHY and the MAC layer at each node's Idle time with the Idle time mechanism state before the proposed function is executed. The Current Control Level of the Report Attribute is fixed at one sending / receiving node where power consumption can occur, by changing Sleep-Wakeup time, the low power consumption efficiency was improved while satisfying the transmission requirement of the given delay time constraint.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.1
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• pp.3-15
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• 1996

An approximation algorithm is presented for cyclic queueing networks with finite buffers. The algorithm decomposes the queueing network into individual queues with revised arrival and service process and revised queue capacity. Then, each queue is analyzed in isolation. The service process reflects the additional delay a unit might undergo due to blocking and the arrival process is described by a 2-phases Coxian ($C_2$) distribution. The individual queues are modelled as $C_2/C_2$/1/B queues. The parameters of the individual queues are computed approximately using an iterative scheme. The population constraint of the closed network is taken into account by ensuring that the sum of the average queue lengths of the individual queues is equal to the number of customers of the network. Extensive numerical experiments show that this method provides a fairly good estimation of the throughput.

• Journal of Korea Multimedia Society
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• v.1 no.1
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• pp.18-25
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• 1998

The basic requirements of distributed multimedia systems are intramedia synchronization which asks the strict delay and jitter for the check period of media buffer and the scaling duration with periodic continuous media such as audio and video media, and intermedia synchronization that needs the constraint for relative time relations among them when several media are presented in parallel. In this paper, a distributed intermedia synchronization algorithm that solves the intermedia synchronization problem by using variable service rates based on the fuzzy logic is designed and then the performance is evaluated through simulation.

• ETRI Journal
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• v.33 no.5
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• pp.759-769
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• 2011

Cooperative hybrid-automatic repeat request (HARQ) protocols, which can exploit the spatial and temporal diversities, have been widely studied. The efficiency of cooperative HARQ protocols is higher than that of cooperative protocols because retransmissions are only performed when necessary. We classify cooperative HARQ protocols as three decode-and-forward-based HARQ (DF-HARQ) protocols and two amplified-and-forward-based HARQ (AF-HARQ) protocols. To compare these protocols and obtain the optimum parameters, two unified frameworks are developed for protocol analysis. Using the frameworks, we can evaluate and compare the maximum throughput and outage probabilities according to the SNR, the relay location, and the delay constraint. From the analysis we can see that the maximum achievable throughput of the DF-HARQ protocols can be much greater than that of the AF-HARQ protocols due to the incremental redundancy transmission at the relay.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.24 no.65
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• pp.89-102
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• 2001

In this paper, the aircraft route scheduling consists of two steps; the pairing generation and the aircraft assignment. The pairing generation is heuristic approach how flights construct pairings from and to the main base. The aircraft resource assignment which is to establish a aircraft route schedule is constructed by constraint satisfaction problem technique. ILOG solver and schedule is used to solve this problem. In addition, a aircraft route reschedule process against departure-arrival delay or aircraft maintenance schedule change is added by partial constraints satisfaction problem technique. Also, Gantt chart made by ILOG views is used to show aircraft route schedule results more easily.

• Journal of IKEEE
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• v.22 no.4
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• pp.1210-1213
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• 2018

In this paper, we propose a method to reduce the amount of current through the Timing Control of the duty cycle and the Report Attribute Control at the MAC Layer in consideration of the Sleep Mode under the IoT wireless environment. The use of a duty cycle is an effective way to reduce energy consumption on wireless sensor networks where the node is placed in sleep mode periodically. In particular, we studied how to control power efficiency through duty rate in Short Transition Time and ACK Time processing while satisfying radio channel limitation criterion. When comparing before and after the improvement considering the delay time constraint, we validated the correlation of the electrical current reduction.

• Journal of the Korea Society of Computer and Information
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• v.10 no.3 s.35
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• pp.11-18
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• 2005

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint. This algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by $62.2\%$ than those of DDMAP. And reduced the number of CLBs by $17.6\%$ than those of TEMPLA.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.35-46
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm. a given logic equation is constructed as the DAG type. then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also. after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within Cl.B. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time much more than the TMCPLD.

• Journal of Communications and Networks
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• v.14 no.4
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• pp.374-384
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• 2012

Utilizing artificial noise (AN) is a good means to guarantee security against eavesdropping in a multi-inputmulti-output system, where the AN is designed to lie in the null space of the legitimate receiver's channel direction information (CDI). However, imperfect CDI will lead to noise leakage at the legitimate receiver and cause significant loss in the achievable secrecy rate. In this paper, we consider a delayed feedback system, and investigate the impact of delayed CDI on security by using a transmit beamforming and AN scheme. By exploiting the Gauss-Markov fading spectrum to model the feedback delay, we derive a closed-form expression of the upper bound on the secrecy rate loss, where $N_t$ = 2. For a moderate number of antennas where $N_t$ > 2, two special cases, based on the first-order statistics of the noise leakage and large number theory, are explored to approximate the respective upper bounds. In addition, to maintain a constant signal-to-interferenceplus-noise ratio degradation, we analyze the corresponding delay constraint. Furthermore, based on the obtained closed-form expression of the lower bound on the achievable secrecy rate, we investigate an optimal power allocation strategy between the information signal and the AN. The analytical and numerical results obtained based on first-order statistics can be regarded as a good approximation of the capacity that can be achieved at the legitimate receiver with a certain number of antennas, $N_t$. In addition, for a given delay, we show that optimal power allocation is not sensitive to the number of antennas in a high signal-to-noise ratio regime. The simulation results further indicate that the achievable secrecy rate with optimal power allocation can be improved significantly as compared to that with fixed power allocation. In addition, as the delay increases, the ratio of power allocated to the AN should be decreased to reduce the secrecy rate degradation.