• Title/Summary/Keyword: Deflection Self-routing

Search Result 4, Processing Time 0.019 seconds

Multidimensional Ring-Delta Network: A High-Performance Fault-Tolerant Switching Networks (다차원 링-델타 망: 고성능 고장감내 스위칭 망)

  • Park, Jae-Hyun
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.35 no.1B
    • /
    • pp.1-7
    • /
    • 2010
  • In this paper, a high-performance fault-tolerant switching network using a deflection self-routing was proposed. From an abstract algebraic analysis of the topological properties of the Delta network, which is a baseline switching network, we derive the Multidimensional Ring-Delta network: a multipath switching network using a deflection self-routing algorithm. All of the links including already existing links of the Delta network are used to provide the alternate paths detouring faulty/congested links. We ran a simulation analysis under the traffic loads having the non-uniform address distributions that are usual in Internet. The throughput of $1024\;{\times}\;1024$ switching network proposed is better than that of the 2D ring-Banyan network by 13.3 %, when the input traffic load is 1.0 and the hot ratio is 0.9. The reliability of $64\;{\times}\;64$ switching network proposed is better than that of the 2D ring-Banyan network by 46.6%.

A High-Performance Fault-Tolerant Switching Network and Its Fault Diagnosis (고성능 결함감내 스위칭 망과 결함 진단법)

  • 박재현
    • Journal of KIISE:Information Networking
    • /
    • v.31 no.3
    • /
    • pp.335-346
    • /
    • 2004
  • In this paper, we present a high-performance fault-tolerant switching networks using a deflection self-routing scheme, and present fault-diagnosis method for the network. We use the facts: 1) Each stage of the Banyan network is arrayed as the sequences of a Cyclic group of SEs. 2) There is the homomorphism between adjacent stages from a view of self-routing, so that all of each Cyclic group is the subgroup of the Cyclic group in the next stage, and there are factor groups due to such subgroup and homomorphism. We provide high-performance fault-tolerant switching networks of which the all links including augmented links are used as the alternate links detouring faulty links. We also present the fault diagnosis scheme for the proposed switching network that provide multiple paths for each input-output pair.

Reliability Analysis of the 2-Dimensional Ring-Banyan Network (2차원 링-밴얀 망의 신뢰성 분석)

  • Park, Jae-Hyun
    • Journal of KIISE:Information Networking
    • /
    • v.34 no.4
    • /
    • pp.256-261
    • /
    • 2007
  • 2-Dimensional Ring-banyan network is a high-performance fault-tolerant switching network using a deflection self-routing. The throughput of the switching network is better than that of Cyclic Banyan network under non-uniform traffic. In this paper, we present an analytic reliability analysis of the fault-tolerant switching network. We present the Mean-Time-to-Failure that is calculated by using probabilistic model. This model also takes into account a hardware complexity. In case of $16\;{\times}\;16$ size, the presented switching network is 1.275 times more reliable than Hui's switching network. And it is 1.510 times more reliable than Hui's network in case of $64\;{\times}\;64$ size.

The Cell Resequencing Buffer for the Cell Sequence Integrity Guarantee for the Cyclic Banyan Network (사이클릭 벤얀 망의 셀 순서 무결성 보장을 위한 셀 재배열 버퍼)

  • 박재현
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.41 no.9
    • /
    • pp.73-80
    • /
    • 2004
  • In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.