• ETRI Journal
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• v.28 no.3
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• pp.389-392
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• 2006

In this letter, a laterally-driven bistable electromagnetic microrelay is designed, fabricated, and tested. The proposed microrelay consists of a pair of arch-shaped leaf springs, a shuttle, and a contact bar made from silicon, low temperature oxide (LTO), and gold composite materials. Silicon-on-insulator wafers are used for electrical isolation and releasing of the moving microstructures. The high-aspect-ratio microstructures are fabricated using a deep reactive ion etching (DRIE) process. The tandem-typed leaf springs with a silicon/gold composite layer enhance the mechanical performances while reducing the electrical resistance. A permanent magnet is attached at the bottom of the silicon substrate, resulting in the generation of an external magnetic field in the direction vertical to the surface of the silicon substrate. The leaf springs show bistable characteristics. The resistance of the pair of leaf springs was $7.5\;{\Omega}$, and the contact resistance was $7.7\;{\Omega}$. The relay was operated at ${\pm}0.12\;V$.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.31 no.6 s.261
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• pp.679-685
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• 2007

Superhydrophobic surface, with a water contact angle greater than $150^{\circ}$, has a self-cleaning effect termed 'Lotus effect'. This surface is created by the combination of rough surface and the low surface energy. We proposed square pillar and square shapes to control surface roughness. Microstructure arrays are fabricated by DRIE(Deep Reactive Ion Etching) process and followed by PPFC(Plasma Polymerized Fluorocarbon) deposition. On the experimental result, contact angle at square pillar arrays is well matched with Cassie's model and largest contact angle is $173.37^{\circ}$. But contact angle of square pore shape arrays is lower than Cassie's theoretical contact angle about $5{\sim}10%$. Nevertheless, square pore arrays have more rigidity than square pillar arrays.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.38.2-38.2
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• 2009

마이크로노즐은 우주공간에서 인공위성의 자세를 바로잡는 데 필요한 마이크로 로켓에 들어가는 필수적인 부품이다. 마이크로 노즐은 또한 나노입자 적층 시스템(nano-particle deposition system, NPDS)에 들어갈 수 있다. NPDS는 세라믹 또는 금속 나노분말 입자를 노즐을 통해 초음속으로 가속시킨 뒤 상온에서 이를 기판에 적층시키는 새로운 시스템이다. 본 연구의 목표는 NPDS에 쓰이는 노즐을 일반적인 반도체 공정을 이용하여 마이크론 스케일의 목을 갖도록 한 마이크로노즐을 제작하는 데 있다. 보쉬 공정은 이러한 마이크로노즐을 제작하는데 필수적인 공정으로, 유도결합플라즈마를 이용해 실리콘 웨이퍼를 식각시키는 기술을 말한다. 보쉬 공정에 사용되는 플라즈마 기체는 $SF_6$와 $C_4F_8$인데, 이 두 가지 기체를 번갈아가면서 사용하여 실리콘 웨이퍼를 이방성 식각하는 것이 그 특징이다. 보쉬 공정에는 다양한 변수가 존재하며 이를 적절히 통제하면 마이크로노즐에 적합한 프로파일을 실리콘 웨이퍼 내에 형성시킬 수 있다. 본 연구에서는 보쉬 공정을 이용하여 3차원 마이크로 노즐을 제작하였다. 기존에 반응성이온식각(deep reactive ion etching, DRIE) 공정을 통해 마이크로노즐을 제작한 사례가 많이 보고되었지만 이들은 모두 2차원적으로 마이크로노즐을 제작하였다. 2차원적으로 제작한 마이크로노즐은 마이크로 로켓에 주로 사용되었지만, 초음속으로 가속된 분말이 노즐의 형상으로 인한 유체 흐름의 불안정성 때문에 NPDS에서는 오래도록 사용할 수 없다는 문제점이 있다. 그러므로 본 연구에서는 마이크로노즐을 3차원 형상으로 제작함으로써 이러한 문제점을 해결하고자 하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.362-369
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• 2011

In this paper, optimal deep reactive ion etching (DRIE) process conditions for fused quartz were experimentally determined by Taguchi method, and fused quartz-based micro cantilevers were fabricated. In addition, comparative study on Q-factors of fused quartz and silicon micro cantilevers was performed. Using a silicon layer as an etch mask for fused quartz DRIE process, different 9 flow rate conditions of $C_4F_8$, $O_2$ and He gases were tested and the optimum combination of these factors was estimated. Micro cantilevers based on fused quartz were fabricated from this optimal DRIE condition. Through conventional silicon DRIE process, single-crystalline silicon micro cantilevers whose dimensions were similar to those of quartz cantilevers were also fabricated. Mechanical Q-factors were calculated to compare intrinsic damping properties of those two materials. Resonant frequencies and Q-factors were measured for the cantilevers having fixed widths and thicknesses and different lengths. The Q-factors were in a range of 64,000 - 108,000 for fused quartz cantilevers and 31,000 - 35,000 for silicon cantilevers. The experimental results supported that fused quartz had a good intrinsic damping property compared to that of single crystalline silicon.

• Applied Microscopy
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• v.50
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• pp.17.1-17.9
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• 2020

Recent advances in fabrication have enabled radial-junction architectures for cost-effective and high-performance optoelectronic devices. Unlike a planar PN junction, a radial-junction geometry maximizes the optical interaction in the three-dimensional (3D) structures, while effectively extracting the generated carriers via the conformal PN junction. In this paper, we report characterizations of radial PN junctions that consist of p-type Si micropillars created by deep reactive-ion etching (DRIE) and an n-type layer formed by phosphorus gas diffusion. We use electron-beam induced current (EBIC) microscopy to access the 3D junction profile from the sidewall of the pillars. Our EBIC images reveal uniform PN junctions conformally constructed on the 3D pillar array. Based on Monte-Carlo simulations and EBIC modeling, we estimate local carrier separation/collection efficiency that reflects the quality of the PN junction. We find the EBIC efficiency of the pillar array increases with the incident electron beam energy, consistent with the EBIC behaviors observed in a high-quality planar PN junction. The magnitude of the EBIC efficiency of our pillar array is about 70% at 10 kV, slightly lower than that of the planar device (≈ 81%). We suggest that this reduction could be attributed to the unpassivated pillar surface and the unintended recombination centers in the pillar cores introduced during the DRIE processes. Our results support that the depth-dependent EBIC approach is ideally suitable for evaluating PN junctions formed on micro/nanostructured semiconductors with various geometry.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.17-21
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• 2007

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.389-390
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• 2012

In this study, we fabricate a superhydrophobic surface made of hierarchical nanostructures that combine wax crystalline structure with moth-eye structure using vacuum cluster system and measure their hydrophobicity and durability. Since the lotus effect was found, much work has been done on studying self-cleaning surface for decades. The surface of lotus leaf consists of multi-level layers of micro scale papillose epidermal cells and epicuticular wax crystalloids [1]. This hierarchical structure has superhydrophobic property because the sufficiently rough surface allows air pockets to form easily below the liquid, the so-called Cassie state, so that the relatively small area of water/solid interface makes the energetic cost associated with corresponding water/air interfaces smaller than the energy gained [2]. Various nanostructures have been reported for fabricating the self-cleaning surface but in general, they have the problem of low durability. More than two nanostructures on a surface can be integrated together to increase hydrophobicity and durability of the surface as in the lotus leaf [3,5]. As one of the bio-inspired nanostructures, we introduce a hierarchical nanostructure fabricated with a high vacuum cluster system. A hierarchical nanostructure is a combination of moth-eye structure with an average pitch of 300 nm and height of 700 nm, and the wax crystalline structure with an average width and height of 200 nm. The moth-eye structure is fabricated with deep reactive ion etching (DRIE) process. $SiO_2$ layer is initially deposited on a glass substrate using PECVD in the cluster system. Then, Au seed layer is deposited for a few second using DC sputtering process to provide stochastic mask for etching the underlying $SiO_2$ layer with ICP-RIE so that moth-eye structure can be fabricated. Additionally, n-hexatriacontane paraffin wax ($C_{36}H_{74}$) is deposited on the moth-eye structure in a thermal evaporator and self-recrystallized at $40^{\circ}C$ for 4h [4]. All of steps are conducted utilizing vacuum cluster system to minimize the contamination. The water contact angles are measured by tensiometer. The morphology of the surface is characterized using SEM and AFM and the reflectance is measured by spectrophotometer.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.31-36
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• 2015

The demand for multi-functionality, high density, high performance, and miniaturization of IC devices has caused the technology paradigm shift for electronic packaging. So, thermal management of new packaged chips becomes a bottleneck for the performance of next generation devices. Among various thermal solutions such as heat sink, heat spreader, TIM, thermoelectric cooler, etc. on-chip liquid cooling module was investigated in this study. Micro-channel was fabricated on Si wafer using a deep reactive ion etching, and 3 different micro-channel designs (straight MC, serpentine MC, zigzag MC) were formed to evalute the effectiveness of liquid cooling. At the heating temperature of $200^{\circ}C$ and coolant flow rate of 150ml/min, straight MC showed the high temperature differential of ${\sim}44^{\circ}C$ after liquid cooling. The shape of liquid flowing through micro-channel was observed by fluorescence microscope, and the temperarue differential of liquid cooling module was measuremd by IR microscope.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.27-31
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• 2015

Thermal management becomes a key technology as the power density of high performance and high density devices increases. Conventional heat sink or TIM methods will be limited to resolve thermal problems of next-generation IC devices. Recently, to increase heat flux through high powered IC devices liquid cooling system has been actively studied. In this study a chip-level liquid cooling system with TSV and microchannel was fabricated on Si wafer using DRIE process and analyzed the cooling characteristics. Three different TSV shapes were fabricated and the effect of TSV shapes was analyzed. The shape of liquid flowing through microchannel was observed by fluorescence microscope. The temperature differential of liquid cooling system was measured by IR microscope from RT to $300^{\circ}C$.