• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.7 no.4
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• pp.223-228
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• 2014

It is known that a belief propagation algorithm is a fast decoding scheme for LT codes but it require a large overhead, especially for a short block length LT codes. In this paper an improved belief decoding algorithm using searching method for degree-1 packets is proposed for a small overhead. The proposed decoding scheme shows the desirable performance in terms of overhead while guaranteeing the same computational complexity with respect to the conventional BP decoding scheme.

• Journal of Information Processing Systems
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• v.13 no.4
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• pp.1029-1042
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• 2017

A joint channel estimation and data detection technique for a multiple input multiple output (MIMO) wireless communication system is proposed. It combines the least square (LS) training based channel estimation (TBCE) scheme with sphere decoding. In this new approach, channel estimation is enhanced with the help of blind symbols, which are selected based on their correctness. The correctness is determined via sphere decoding. The performance of the new scheme is studied through simulation in terms of the bit error rate (BER). The results show that the proposed channel estimation has comparable performance and better computational complexity over the existing semi-blind channel estimation (SBCE) method.

• Journal of Korea Multimedia Society
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• v.2 no.1
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• pp.38-46
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• 1999

In this paper, the fractal image compression using the minimizing method of domain region is proposed. It is minimize to domain regions in the process of decoding. Since the conventional fractal decoding applies to IFS(iterative function system) for the total range blocks of the decoded image, its computational complexity is a vast amount. In order to improve this using the number of the referenced times to the domain blocks for the each range blocks, a classification method which divides necessary and unnecessary regions for IFS is suggested. If necessary regions for IFS are reduced, the computational complexity is reduced. The proposed method is to define the minimum domain region that a necessary region for IFS is minimized in the encoding algorithms. That is, a searched region of the domain is limited to the range regions that is similar with the domain regions. So, the domain region is more overlapped. Therefore, there is not influence on image quality or PSNR(peak signal-to-noise ratio). And it can be a fast decoding by reduce the computational complexity for IFS in fractal image decoding.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.118-126
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• 2003

This paper presents a low-complexity algorithm lot browsing a HD bit stream in DTV PVR according to its characteristics and also presents its implementation results. We propose an efficient algorithm which detects shots using some information after decoding MPEG-2 data, clusters them into scene and episode, and intelligently browses them according to some criteria after calculating their complexity. Some simulation results are presented to show the performance feasibility of the proposed algorithm. To implement it in real time, we propose an efficient hybrid architecture which partitions the algorithm into two parts of hardware and software. The hardware covers decoding process and extraction of some basic information which take most complexity in implementing the algorithm. The software covers the heuristic part of tile algorithm which has low complexity and needs to be expandable.

• ETRI Journal
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• v.32 no.4
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• pp.588-595
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• 2010

This paper proposes encoding and decoding for nonlinear product codes and investigates the performance of nonlinear product codes. The proposed nonlinear product codes are constructed as N-dimensional product codes where the constituent codes are nonlinear binary codes derived from the linear codes over higher order alphabets, for example, Preparata or Kerdock codes. The performance and the complexity of the proposed construction are evaluated using the well-known nonlinear Nordstrom-Robinson code, which is presented in the generalized array code format with a low complexity trellis. The proposed construction shows the additional coding gain, reduced error floor, and lower implementation complexity. The (64, 24, 12) nonlinear binary product code has an effective gain of about 2.5 dB and 1 dB gain at a BER of $10^{-6}$ when compared to the (64, 15, 16) linear product code and the (64, 24, 10) linear product code, respectively. The (256, 64, 36) nonlinear binary product code composed of two Nordstrom-Robinson codes has an effective gain of about 0.7 dB at a BER of $10^{-5}$ when compared to the (256, 64, 25) linear product code composed of two (16, 8, 5) quasi-cyclic codes.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.42-49
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• 2016

This paper proposes a low-complexity generator which finds the first two minimum values using bit-serial scheme. A low-complexity generator is an important part for low-area LDPC decoders based on the min-sum decoding algorithm because the hardware complexity of generators utilizes a significant portion of LDPC decoders. To reduce hardware complexity, bit-serial LDPC decoders has been studied. The generator of the existing bit-serial LDPC decoders can find only the first minimum value, and thus it leads to a BER performance degradation. The proposed generator using bit-serial scheme finds the first two minimum values. Hence, it can improve the BER performance. In addition, the area-time complexity of the proposed generator is lower than those of the existing generators finding the first two minima.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.523-529
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• 2017

In this paper, we propose an efficient sphere decoding scheme that reduces computational complexity by combining receive and transmit ordering techniques in generalized spatial modulation systems, where the indexes of activated transmit antennas as well as the transmit symbols are exploited to transfer information to the receiver. In this scheme, the receive signals are optimally ordered so that the calculation for a candidate solution outside the sphere is terminated early to lower the computational complexity. In addition, the transmit ordering technique is applied to first search for candidate symbols and activated antennas having higher probabilities to further reduce the computational complexity. Simulation results show that the proposed doubly ordered sphere decoding scheme provides the same bit error rate performance with the conventional sphere decoding method and the sphere decoder employing only the receive ordering technique while it requires lower computational complexity.

• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2197-2204
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• 2009

In this paper, we analyze the performance of the sphere decoding algorithm at MIMO system. The BER performance of this algorithm is the same as that of ML receiver, but computational complexity of SD algorithm is much less than that of ML receiver. The independent signals from each transmit antennas are modulated by using the QPSK and 16QAM modulation in the richly scattered Rayleigh flat-fading channel. The received signals from each receivers is independently detected by the receiver using Fincke & Pohst SD algorithm, and the BER output of the algorithm is compared with those of ZF, MMSE, SIC, and ML receivers. We also investigate the Viterbo & Boutros SD algorithm which is the modified SD algorithm, and the BER performance and the floting point operations of the algorithms are comparatively studied.