• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.4
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• pp.1-9
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• 2008

This paper presents a rapid watermarking algorithm based on DC image, which provides a resilience to geometric distortion. Our proposed scheme is based on $8{\times}8$ block DCT that is widely used in image/video compression techniques (e.g., JPEG and MPEG). In particular, a DC image is analyzed by DWT to embed a watermark. To overcome a quality degradation caused by a watermark insertion into DC components, we discern carefully the intensity and amount of watermark along the different subbands of DWT. Note that the proposed technique supports a high throughput for a real-time watermark insertion and extraction by relying on a partial decoding (i.e., DC components) on $8{\times}8$ block DCT domain. Experimental result shows that the proposed watermarking scheme significantly reduces computation time of 82% compared with existing DC component based algorithm and yet provides invariant properties against various attacks such as geometric distortion and JPEG compression, etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.34-42
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• 2012

Low density parity check (LDPC) code is widely used, since it shows superior performance close to Shannon limit and its decoding complexity is lower than turbo code. Recently, it is used as a channel code to decode Wyner-Ziv frames in distributed video coding (DVC) system. In this paper, we propose an efficient method to design the parity check matrix H of LDPC codes. In order to apply LDPC code to DVC system, the LDPC code should have rate compatibility. Thus, we also propose a method to merge check nodes of LDPC code to attain the rate compatibility. LDPC code is designed using ACE algorithm and check nodes are merged for a given code rate to maximize the error correction capability. The performance of the designed LDPC code is analyzed extensively by computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9C
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• pp.537-545
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• 2011

This paper analyzed performance of three dimensional turbo code and turbo ${\Phi}$ codes proposed in the next generation DVB-RCS systems. In the view of turbo ${\Phi}$ codes, we proposed the optimal permutation and puncturing patterns for triple binary input data. We also proposed optimal post-encoder types and interleaving algorithm for three dimensional turbo codes. Based on optimal parameters, we simulated both turbo codes, and we confirmed that the performance of turbo ${\Phi}$ codes are better than that of three dimensional turbo codes. However, the complexity of turbo ${\Phi}$ is more complex than that of three dimensional turbo codes by 18%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.10C
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• pp.1000-1010
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• 2006

This paper proposes a new architecture for DCT-based motion estimation and compensation. Previous methods do riot take sufficient advantage of the sparseness of 2-D DCT coefficients to reduce execution time. We first derive a recursion equation to perform DCT domain motion estimation more efficiently; we then use it to develop a wavefront array processor (WAP) consisting of processing elements. In addition, we show that the recursion equation enables motion predicted images with different frequency bands, for example, from the images with low frequency components to the images with low and high frequency components. The wavefront way Processor can reconfigure to different motion estimation algorithms, such as logarithmic search and three step search, without architectural modifications. These properties can be effectively used to reduce the energy required for video encoding and decoding. The proposed WAP architecture achieves a significant reduction in computational complexity and processing time. It is also shown that the motion estimation algorithm in the transform domain using SAD (Sum of Absolute Differences) matching criterion maximizes PSNR and the compression ratio for the practical video coding applications when compared to tile motion estimation algorithm in the spatial domain using either SAD or SSD.

• International Journal of Aeronautical and Space Sciences
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• v.9 no.2
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• pp.121-128
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• 2008

Modularized GPS software defined radio (SDR) has many advantages of applying and modifying algorithm. Hardware based GPS receiver uses many hardware parts (such as RF front, correlators, CPU and other peripherals) that process tracked signal and navigation data to calculate user position, while SDR uses software modules, which run on general purpose CPU platform or embedded DSP. SDR does not have to change hardware part and is not limited by hardware capability when new processing algorithm is applied. The weakness of SDR is that software correlation takes lots of processing time. However, in these days the evolution of processing power of MPU and DSP leads the competitiveness of SDR against the hardware GPS receiver. This paper shows a study of modulization of GPS software platform and it presents development of the GNSS software platform using MATLAB Simulink™. We focus on post processing SDR platform which is usually adapted in research area. The main functions of SDR are GPS signal acquisition, signal tracking, decoding navigation data and calculating stand alone user position from stored data that was down converted and sampled intermediate frequency (IF) data. Each module of SDR platform is categorized by function for applicability for applying for other frequency and GPS signal easily. The developed software platform is tested using stored data which is down-converted and sampled IF data file. The test results present that the software platform calculates user position properly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.1028-1035
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• 1999

To increase the throughput of data transmission in burst-mode TDMA communication systems and also to get a good BER performance at the same time, it is essential to rapidly acquire the carrier while keeping the desirable tracking performance. To achieve this goal, in this paper, a new decision-directed carrier recovery algorithm is presented. The proposed scheme does not incorporate the PLL and suppress the Gaussian random process of input noise by the pre-stage low pass filter so as to get both the fast acquisition and a good performance. Through computer simulations, the performance of the scheme is analyzed with respect to the acquisition time and bit error rate. The cycle slip in the proposed scheme is seldom observed at very low SNR environment in contrast to the previous proposed one. Because of this merit, it is not required to do the differential encoding and decoding in the proposed scheme.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.3
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• pp.179-187
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• 2000

Fractal theory has strengths such as high compression rate and fast decoding time in application to image compression, but it suffers from long comparison time necessary for finding an optimally similar domain block in the encoding stage. This paper proposes a neural network based block classifier which enhances the encoding time significantly by classifying domain blocks into 4 patterns and searching only those blocks having the same pattern with the range block to be encoded. Size of a block is differently determined depending on the image complexity of the block. The proposed algorithm has been tested with three different images having various featrues. The experimental results have shown that the proposed algorithm enhances the compression time by 40% on average compared to the conventional fractal encoding algorithms, while maintaining allowable image qualify of PSNR 30 dB.

• Journal of Navigation and Port Research
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• v.41 no.4
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• pp.173-180
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• 2017

Underwater communications are degraded as a result of inter symbol interference in multipath channels. Therefore, a channel coding scheme is essential for underwater communications. Packets consist of a PN sequence and a data field, and the uncoded PN sequence is used to estimate the frequency and phase offset using a Doppler and phase estimation algorithm. The estimated frequency and phase offset are fed to a coded data field to compensate for the Doppler and phase offset. The PN sequence is generally utilized to acquire the synchronization information, and the bit error rate of an uncoded PN sequence predicts the performance of the coded data field. To ensure few errors, we resort to powerful BCJR decoding algorithms of convolutional codes with rates of 1/2, 2/3, and 3/4. We use this powerful channel coding algorithm to present an efficient receiver structure based on the relation between the bit error of the uncoded PN sequence and coded data field in computer simulations and lake experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.