• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.115-124
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• 2015

In this paper, the method which improves the performance of a serial decimal multiplier, and the method which operates multiple-digit simultaneously are proposed. The proposed serial decimal multiplier reduces the delay by removing encoding module that generates 2X, 4X multiples, and by generating partial product using shift operation. Also, this multiplier reduces the number of operations using multiple-digit operation. In order to estimate the performance of the proposed multiplier, we synthesized the proposed multiplier with design compiler with SMIC 110nm CMOS library. Synthesis results show that the area of the proposed serial decimal multiplier is increased by 4%, but the delay is reduced by 5% compared to existing serial decimal multiplier. In addition, the trade off between area and latency with respect to the number of concurrent operations in the proposed multiple-digit multiplier is confirmed.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.50-58
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• 2013

In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion.

• Journal of Elementary Mathematics Education in Korea
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• v.15 no.1
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• pp.1-18
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• 2011

The purpose of this study was to investigate the effects of estimation strategy on placing decimal point in multiplication and division of decimals. To examine the effects of improving calculation ability and reducing decimal point errors with this estimation strategy, the experimental research on operation with decimal was conducted. The operation group conducted the decimal point estimation strategy for operating decimal fractions, whereas the control group used the traditional method with the same test paper. The results obtained in this research are as follows; First, the estimation strategy with understanding a basic meaning of decimals was much more effective in calculation improvement than the algorithm study with repeated calculations. Second, the mathematical problem solving ability - including the whole procedure for solving the mathematical question - had no effects since the decimal point estimation strategy is normally performed after finishing problem solving strategy. Third, the estimation strategy showed positive effects on the calculation ability. Th Memorizing algorithm doesn't last long to the students, but the estimation strategy based on the concept and the position of decimal fraction affects continually to the students. Finally, the estimation strategy assisted the students in understanding the connection of the position of decimal points in the product with that in the multiplicand or the multiplier. Moreover, this strategy suggested to the students that there was relation between the placing decimal point of the quotient and that of the dividend.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.56-65
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.20-35
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• 2016

In this paper, in order to reduce the delay and area of the partial product accumulation (PPA) of the parallel decimal multiplier, a tree architecture that composed by multi-operand decimal CSAs and improved CLA is proposed. The proposed tree using multi-operand CSAs reduces the partial product quickly. Since the input range of the recoder of CSA is limited, CSA can get the simplest logic. In addition, using the multi-operand decimal CSAs to add decimal numbers that have limited range in specific locations of the specific architecture can reduce the partial products efficiently. Also, final BCD result can be received faster by improving the logic of the decimal CLA. In order to evaluate the performance of the proposed partial product accumulation, synthesis is implemented by using Design Complier with 180 nm COMS technology library. Synthesis results show the delay of the proposed partial product accumulation is reduced by 15.6% and area is reduced by 16.2% comparing with which uses general method. Also, the total delay and area are still reduced despite the delay and area of the CLA are increased.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.6
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• pp.55-60
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• 2023

When performing the multiplication m×r=p of two binary numbers m and r on a computer, there is a shift-and-add(SA) method in which no time-consuming multiplication is performed, but only addition and shift-right(SR). SA is a very simple method in which when the value of the multiplier r_i is 0, the result p is only SR with m×0=0, and when r_i is 1, the result p=p+m is performed with m×1=m, and p is SR. In SA, the number of SRs can no longer be shortened, and the improvement part is whether the number of additions is shortened. This paper proposes an SA method to minimize addition based on the fact that setting a smaller number to r when converted to a binary number to be processed by a computer can significantly reduce the number of additions compared to the case of setting a smaller number to r based on the decimals that humans perform. The number of additions to the proposed algorithm was compared for four cases with signs (-,-), (-,+), (+,-), and (+,+) for some numbers in the range [-127,128]. The conclusion obtained from the experiment showed that when determining m and r, it should be determined as a binary number rather than a decimal number.