• Broadcasting and Media Magazine
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• v.15 no.4
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• pp.66-76
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• 2010

HEVC(High Efficiency Video Coding)는 현재 표준화가 진행되고 있는 새로운 비디오 부호화 표준의 가칭이다. 이 표준화에서는 H.264/AVC를 넘어선 높은 부호화 성능을 갖기 위해서 다양한 방법들이 논의되고 있으며, 그 중에서 deblocking filter 및 adaptive loop filter 기술에 대해 본 고에서 설명하고자 한다. 기술적으로 deblokcing 필터와 adaptive loop filter는 양자화 및 부호화 연산과 정에서 손실되는 정보를 줄이기 위해 복원된 영상에 필터링을 수행함으로써주관적화질을향상시키기위한기술이다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.19-26
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• 2005

After various video coding standards such as H.263, MPEG-4, and H.264 have been introduced, there has bun strong need to support the multiple standards with limited resources efficiently. In terms of deblocking Inter which plays an important role in improving visual quality, K264 deblocking filter implementation has different aspects as compared with traditional $8\times8$ block-based post-filter implementation. Analyzing the differences, this paper proposes a H.264 deblocking filter implementation method that supports $8\times8$ block-based post-filtering for the traditional video coding systems. In the proposed implementation method the block boundaries to he filtered are adaptively chosen for $8\times8$ and $4\times4$ block boundary filtering. Since the filtered result is selectively used for motion compensation or not, both loop-filtering and post-filtering can be achieved. A quantization parameter conversion unit that converts H.263 quantization parameters to H.264 quantization parameters is utilized by examining the $8\times8$ block boundary errors based on human visual system. Since the original nature of the H.264 deblocking filter is well expanded to the $8\times8$ block-based post-filter with minor modifications, the proposed implementation method is suitable to implement the deblocking function of the multiple video standards such as H.263, MPEG-4, and K264, efficiently.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.6
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• pp.30-35
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• 2007

H.264/AVC provides better quality than other algorithms by using a deblocking filter to remove blocking distortion on block boundary of the decoded picture. However, this filtering process includes lots of memory accesses, which cause delay of overall decoding time. In this paper, we propose a data-reuse algorithm to speed up the process for the deblocking filter. To reuse the data, a new filtering order is suggested. By using this order, we reduce the memory access and accelerate the deblocking filter. The modeling of proposed algorithm is compiled under ARM ADS1.2 and simulated with Armulator. The results of the experiment compared with H.264/AVC standard are achieved on average 58.45% and 57.93% performance improvements at execution cycles and memory access cycles, respectively.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.742-755
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• 2012

In this paper, we propose a parallel deblocking algorithm to resolve workload imbalance when the deblocking filter of high efficiency video coding (HEVC) decoder is parallelized. In HEVC, the deblocking filter which is one of the in-loop filters conducts two-step filtering on vertical edges first and horizontal edges later. The deblocking filtering can be conducted with high-speed through data-level parallelism because there is no dependency between adjacent edges for deblocking filtering processes. However, workloads would be imbalanced among regions even though the same amount of data for each region is allocated, which causes performance loss of decoder parallelization. In this paper, we solve the problem for workload imbalance by predicting the complexity of deblocking filtering with coding unit (CU) depth information at a coding tree block (CTB) and by allocating the same amount of workload to each core. Experimental results show that the proposed method achieves average time saving (ATS) by 64.3%, compared to single core-based deblocking filtering and also achieves ATS by 6.7% on average and 13.5% on maximum, compared to the conventional uniform data-level parallelism.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.662-672
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• 2011

This paper presents a new edge-preserving algorithm and its VLSI architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-preserving maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is prototyped on FPGA Cyclone II, and then we estimated performance when the filter is synthesized on ANAM 0.25 ${\mu}m$ CMOS cell library using Synopsys Design Compiler. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• ETRI Journal
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• v.32 no.3
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• pp.380-389
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• 2010

This paper presents a new edge-protection algorithm and its very large scale integration (VLSI) architecture for block artifact reduction. Unlike previous approaches using block classification, our algorithm utilizes pixel classification to categorize each pixel into one of two classes, namely smooth region and edge region, which are described by the edge-protection maps. Based on these maps, a two-step adaptive filter which includes offset filtering and edge-preserving filtering is used to remove block artifacts. A pipelined VLSI architecture of the proposed deblocking algorithm for HD video processing is also presented in this paper. A memory-reduced architecture for a block buffer is used to optimize memory usage. The architecture of the proposed deblocking filter is verified on FPGA Cyclone II and implemented using the ANAM 0.25 ${\mu}m$ CMOS cell library. Our experimental results show that our proposed algorithm effectively reduces block artifacts while preserving the details. The PSNR performance of our algorithm using pixel classification is better than that of previous algorithms using block classification.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.11a
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• pp.74-76
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• 2017

In this paper, we introduce the CNN-based in-loop technology for HEVC, and analyze the performance of these algorithms through comparative experiments. The current in-loop filters in HEVC are composed of a deblocking filter that removes noise and a sample adaptive offset filter that compensates for signal offsets. A couple of CNN-based filters replacing the roles of these two algorithms are selected and compared.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.890-893
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• 2006

동영상과 관련된 멀티미디어가 많은 관심을 받으며 영상 압축 기술에 대한 관심이 높아지고 있는 가운데, 최근 다른 표준보다 두 배 이상 좋은 새로운 비디오 코딩 표준인 H.264/AVC의 압축 기술이 발표되었다. 이 기술은 지상파 DMB와 PMP, 카메라폰 그리고 핸드폰의 게임과 음악 및 영상에 관련된 컨텐츠에서 고품질의 영상을 보다 효율적으로 제공한다. 이에 본 논문에서는 H.264/AVC의 부호화 과정에서 발생하는 오류로 인한 블록화를 최소화하기 위해 사용되는 deblocking 필터의 메모리와 처리속도의 향상을 제안하였다. 27*32SRAM을 사용하여 Vertical edge를 모두 처리하고 Horizontal edge를 처리하는 방식이 아닌 한 블록에 대한 Vertical edge후에 바로 Horizontal edge를 처리함으로써 28(prebuffering)19(Y)+32(Cb)+32(Cr)=188clocks에 $16\times16$ 블록 처리가 완료되는 deblocking 필터를 제안하여 하드웨어 설계언어인 VHDL언어로 설계하였다. 그리고 FPGA칩인 XCV1000E에 다운로드하여 칩 레벨의 시뮬레이션을 수행함으로써 설계된 deblocking 필터를 검증하였다.