• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.1
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• pp.45-52
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• 2021

The space vector control based voltage control method for a three-phase PWM rectifier requires a lot of effort to design an optimal switching pattern since a switching pattern for the switching section must be designed. In this study, a D-Q control based SPWM output voltage control algorithm was studied for the three-phase six-pulse CVS type rectifier. In the output voltage control algorithm, three-phase reference signals are obtained from the D-Q transformation based on the space vector representation method, instead of the switching pattern, SPWM method is used to generate rectifier switching control signals. Next, a three-phase six-pulse CVS PWM rectifier based on D-Q transformation and SPWM was modeled using EMTP-RV. Finally, the validity of the D-Q control-based SPWM voltage control algorithm was confirmed by comparing the output voltage waveform obtained through EMTP-RV simulation works with a reference value and confirming that the output voltage accurately follows the reference voltage.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2722-2728
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• 2011

3Phase PWM rectifier has become increasingly popular due to its capability of nearly sinusoidal waveform of the input current, and nearly unity power factor operation as a AC/DC rectifier of high capacity telecommunication power supply system. Generally, PI controller is used as a voltage controller of PWM rectifier and voltage controller must be designed to have low overshoot in transient state to get a reliability and stable operation. However, in the application of telecommunication in which load condition is varied very fast, the voltage controller must have a large bandwidth to reduce output voltage variation. The PI controller with large bandwidth arouse the excessive overshoot of the output voltage, and this large output voltage variation degrades the reliability of communication power of the three-phase PWM Rectifier. In this paper, new IP voltage controller for 3 phase PWM rectifier is proposed which has relatively low transient output voltage variation. The improved output characteristics of the transient state voltage responses of the starting and at load changes of the proposed voltage controller are proved by simulations and experiments.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.152-159
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• 2016

This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.360-369
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• 2008

The solar cells should be operated at the maximum power point because its output characteristics were greatly fluctuated on the variation of insolation, temperature and load. It is necessary to install an inverter among electric power converts by means of the output power of solar cell is DC. The inverter is operated supply a sinusoidal current and voltage to the load and the interactive utility line. In this paper, the proposes a photovoltaic system is designed with a step up chopper and single phase PWM voltage source inverter. Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper is operated in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature for solar cell has typical dropping character. The single phase PWM voltage source inverter is consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be develop continuously by connecting with the source of electric power for ordinary using. It can be cause the efect of saving electric power, from 10 to 20%. The single phase PWM voltage source inverter operates in situation, that its output voltage is in same phase with the utility voltage. The inverter are supplies an ac power with high factor and low level of harmonics to the load and the utility power system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of Biomedical Engineering Research
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• v.22 no.5
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• pp.449-458
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• 2001

This is a test report of system efficiency for the moving-actuator type Bi-ventricular assist device (AnyHear $t^{MT}$ ) Seoul National University). $AnyHeart^{TM}$), as an energy converter. utilities a brushless DC motor(S/M 566-26A. Sierracin/ Magnedyne, Carlsbad, CA. U.S.A.) generating their pendulous motion in the epicyclic gear train. It is necessary to know about the overall efficiency of the system. The system is subdivided into three parts: motor part, actuator part and blood sac part (including valves, etc.) according to system mechanism. The motor was operated with a variable range of torque. angular speed and width of voltage Pulse In this report. $AnyHeart^{TM}$ is focused on the efficiency of the motor and actuator parts. 4 $\ell/min$ pump output. which is normal condition of $AnyHeart^{TM}$ system, the total system efficiency is 8%, which is composed of 50%, 85% and 17% efficiency (motor Part, actuator Part and blood sac Part) respectively. In the analyzed result. applied input voltage on normal condition of $AnyHeart^{TM}$ is determined. Also speed Profile with considering filling state of blood sac is Provided. In the test of the in vitro mock circulation. some experimental results are Provided to demonstrate the effectiveness of the Presented approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.4
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• pp.659-666
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• 2006

Servo-motors are used as key components of automated system by performing precise motion control as accurate positioning and accurate speed regulation in response to the commands from computers and sensors. Especially, the linear brushless servo-motors have numerous advantages over the rotary servo motors which have connection with the friction induced transfer mechanism such as ball screws, timing belts, rack/pinion. This paper proposes an estimation method of unknown motor system parameters using the informations from the sinusoidal driving type linear brushless DC motor dynamics and outputs. The estimated parameters can be used to tune the controller gain and a disturbance observer. In order to meet this purpose high performance Digital Signal Processor, TMS320F240, designed originally for implementation of a Field Oriented Control(FOC) technology is adopted as a controller of the liner BLDC servo motor. Having A/D converters, PWM generators, rich I/O port internally, this servo motor application specific DSP play an important role in servo motor controller. This linear BLDC servo motor system also contains IPM(Intelligent Power Module) driver and hail sensor type current sensor module, photocoupler module for isolation of gate signals and fault signals.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.12
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• pp.1380-1393
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• 2010

This paper presents a design, fabrication and the test results of planar active electronically scanned array(AESA) radar prototype for airborne fighter applications using transmit/receive(T/R) module hybrid technology. LIG Nex1 developed a AESA radar prototype to obtain key technologies for airborne fighter's radar. The AESA radar prototype consists of a radiating array, T/R modules, a RF manifold, distributed power supplies, beam controllers, compact receivers with ADC(Analog-to-Digital Converter), a liquid-cooling unit, and an appropriate structure. The AESA antenna has a 590 mm-diameter, active-element area capable of containing 536 T/R modules. Each module is located to provide a triangle grid with $14.7\;mm{\times}19.5\;mm$ spacing among T/R modules. The array dissipates 1,554 watts, with a DC input of 2,310 watts when operated at the maximum transmit duty factor. The AESA radar prototype was tested on near-field chamber and the results become equal in expected beam pattern, providing the accurate and flexible control of antenna beam steering and beam shaping.