• ETRI Journal
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• v.34 no.5
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• pp.727-733
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• 2012

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low-power active matrix organic light-emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level-shifting scheme, the low-data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.428-430
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.544-546
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• Journal of Information Processing Systems
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• v.5 no.4
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• pp.175-186
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• 2009

Power consumed by modern computer systems, particularly servers in data centers has almost reached an unacceptable level. However, their energy consumption is often not justifiable when their utilization is considered; that is, they tend to consume more energy than needed for their computing related jobs. Task scheduling in distributed computing systems (DCSs) can play a crucial role in increasing utilization; this will lead to the reduction in energy consumption. In this paper, we address the problem of scheduling precedence-constrained parallel applications in DCSs, and present two energy- conscious scheduling algorithms. Our scheduling algorithms adopt dynamic voltage and frequency scaling (DVFS) to minimize energy consumption. DVFS, as an efficient power management technology, has been increasingly integrated into many recent commodity processors. DVFS enables these processors to operate with different voltage supply levels at the expense of sacrificing clock frequencies. In the context of scheduling, this multiple voltage facility implies that there is a trade-off between the quality of schedules and energy consumption. Our algorithms effectively balance these two performance goals using a novel objective function and its variant, which take into account both goals; this claim is verified by the results obtained from our extensive comparative evaluation study.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.1-11
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• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.4
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• pp.247-256
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• 2008

Regenerative energy generated by regenerative braking of DC traction can cause the system malfunction or damage to the rectifier, or malfunction of the power conversion device in power supply system by DC Line voltage rise in feeder line. Regenerative energy storage system using super capacitor is one of the ways to stabilize DC line voltage. In this paper, energy storage system of DC traction system using super-capacitor bank is implemented and using the field measurement data of the station N and the station S on the Line 2, the operation characteristics of line voltage caused by regenerative energy of electric trains are verified. Also, charge/discharge characteristics of super capacitor are verified as well. Thus, we can verify the operation characteristics of super-capacitor bank for regenerative energy storage system installed in DC Traction. And if we can use field measurement data of DC line voltage, we have obtained cost reduction. The stabilization of the system will be improved by measuring the operation characteristics of regenerative energy storage system in certain section operated by DC traction and predicting the capacity and lifetime of super-capacitor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.35-42
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• 2005

This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.511-517
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• 2006

The key issues in high power, high energy applications such as electromagnetic launchers include safety, reliability, flexibility, efficiency, compactness, and cost. To explore some of the issues, a control scheme for a large current wave-forming was designed, built and experimentally verified using a 2.4MJ pulse power system (PPS). The PPS was made up of eight capacitors bank unit, each containing six capacitors connected in parallel. Therefore there were 48 capacitors in total, with ratings of 22kV and 50kJ each. Each unit is charged through a charging switch that is operated by air pressure. For discharging each unit has a triggered vacuum switch (TVS) with ratings of 200kA and 250kV. Hence, flexibility of a large current wave-forming can be obtained by controlling the charging voltage and the discharging times. The whole control system includes a personal computer(PC), RS232 and RS485 pseudo converter, electric/optical signal converters and eight 80C196KC micro-controller based capacitor-bank module(CBM) controllers. Hence, the PC based controller can set the capacitor charging voltages and the TVS trigger timings of each CBM controller for the current wave-forming. It also monitors and records the system status data. We illustrated that our control scheme was able to generate the large current pulse flexibly and safely by experiments. The our control scheme minimize the use of optical cables without reducing EMI noise immunity and reliability, this is resulting in cost reduction. Also, the reliability was increased by isolating ground doubly, it reduced drastically the interference of the large voltage pulse induced by the large current pulse. This paper contains the complete control scheme and details of each subsystem unit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.1-7
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• 2007

This paper proposes CMOS semi-digital data recovery with 2X converse oversampling to reduce power consumption and chid area of high definition multimedia interface (HDMI) receivers. Proposed recovery can reduce its power and the effective area by using nt converse oversampling algorithm and semi-digital architecture. Proposed circuit is fabricated using 0.18um CMOS process and measured results demonstrated the power consumption of 14.4mW, the effective area of $0.152mm^2$ and the jitter tolerance of 0.7UIpp with 1.8V supply voltage.)

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.195-206
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• 2004

In an RFID system, it is desirable to have both the reader and the transponder tuned to the same resonant frequency for efficient data transmission between them. Any difference in frequency will decrease the transponder coil voltage or the internal power supply voltage and will increase the possibility of zero modulation in the reader coil, which results in the reduction of the reading distance. In this paper, the phenomena caused by the frequency mismatch are theoretically analyzed and mathematically modelled. Several schemes to compensate for the frequency mismatch are also mentioned. The derived equations and analyzed theory on the data transmission between the reader and the transponder will be helpful to the development of RFID systems for many applications.