• Clean Technology
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• v.8 no.1
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• pp.27-37
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• 2002

To verify the performance and effectiveness of bilinear model for the development of ozone prediction system, the simulation experiments of the model identification for ozone formation were performed by using bilinear and linear models. And the prediction results of the ozone formation by bilinear model were compared to those of linear model and the measured data of Seoul. ARMA(Autoregressive Moving Average) model was used in the model identification. A recursive parameter estimation algorithm based on an equation error method was used to estimate parameters of model. From the results of model identification experiment, the ozone formation by bilinear model showed good agreement with the ozone formation from the simulator. From the comparison of the prediction results and the measured data, it appears that the method proposed in this work is a reasonable means of developing real-time short-term prediction of ozone formation for an ozone forecast system.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.31-37
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• 1997

This paper describes the design and implementation of 8 bit ALU graphic simulator which helps students who study the structure and operation course of general ALU. ALU of this paper consists of three parts, arithmetic circuit, logic circuit, and shifter. Each of them performs as follows. Arithmetic circuit performs arithmetic operation such as addition, subtraction, 1 increment, 1 decrement, 2's complement, logic circuit performs logic operation such as OR, AND, XOR, NOT, and shifter performs shift operation and transfers the result of circuits of arithmetic, logic to data bus. The instructions which relate to these basic ALU functions was selected from Z80 instructions and ALU circuit was designed with those instructions and this designed ALU circuit was implemented on graphic screen. And all state of this data operation course in ALU was showed by bit and logic gate unit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.1-10
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• 2000

A rigorous modeling of ultra-low energy implantation is becoming increasingly more important as devices shrink to deep submicron dimensions. In this paper, we have developed an efficient three-dimensional Monte Carlo ion implantation model based on a modified Binary Collision Approximation(BCA). To this purpose, the modified electronic stopping model and the multi-body collision model have been taken into account in this simulator. The dopant and damage profiles show very good agreement with SIMS(Secondary Ion Mass Spectroscopy) data and RBS(Rutherford Backscattering Spectroscopy) data, respectively. Moreover, the ion distribution replica method has been implemented into the model to get a computational efficiency in a 3D simulation, and we have calculated the 3D Monte Carlo simulation into the topographically complex structure.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.127-136
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• 2008

This paper proposes the efficient system for automatic design of FSS(Frequency Selective Surface) with periodic pattern and frequency characteristics specified by operator. The proposed system derives optimal design parameters through tool for analysis of FSS with arbitrary pattern, DB(Data Base) implemented from limited simulation and measurement data of FSS, and GA(Genetic Algorithm) for optimizing design parameters. FSS analysis tool consists of two analysis tools. One is the simulator for analysis of monolayer FSS that using moment method, another is the tool with approximated analysis method of FSS with dielectric layer. Given pattern configuration and characteristics specified by operators, the DB system searches the best matching FSS, and provides initial genes to GA from the searched parameters, which drastically reduces running time of GA for finding the FSS design parameters. In this paper, the proposed design system is verified through simulation and measurement about FSS with various patterns.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.4
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• pp.40-46
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• 2011

Wireless Sensor Networks(WSNs) have shown a lot of good outcomes in providing a various functions depending on industrial expectations by deploying ad-hoc networking with helps of light loaded and battery powered sensor nodes. In particular, it is strongly requested to develop an algorithm of cross-layer control between 2-layer and 3-layer to deriver the sensing data from the end node to the sink node on time. In this paper, based on the above observation we have proposed an IEEE802.15.4 based self priority routing scheme under UC Berkely TinyOS platform. The proposed beacon based priority routing (BPR) algorithm scheme utilizes beacon periods in sending message with embedding the high priority data and thus provides high quality of service(QoS) in the given criteria. The performance measures are the packet Throughput, delivery, latency, total energy consumption. Simulation results under TinyOS Simulator(TOSSIM) have shown the proposed scheme outcome the conventional Ad hoc On-Demand Distance Vector(AODV) Routing.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.4
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• pp.9-16
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• 2011

This paper represents an interworking architecture for keeping the VLC audio quality between Worldwide Interoperability for Microwave Access (WiMAX) and IEEE 802.11 Mobile Ad hoc Network (MANET) where both mobile routers and mobile nodes are moving dynamically. Systematic performance analysis on the interworking architecture has been conducted by using OPNET simulator to show the results such as Packet Delivery Ratio (PDR) and throughput. Based on simulation results, when the number of MANET nodes is small, PDR remains relatively stable even though data packets increase. However, with the many MANET nodes, PDR decreases as data traffic increases. Throughput is affected by the number of MANET nodes. Especially when the MANET node density has increased further, throughput is much higher, but it is not affected by the mobility speed. However, FTP download and upload response time is not affected much by both the number of MANET nodes and the mobility speed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.12
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• pp.1388-1398
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• 2012

SAR(Synthetic Aperture Radar) systems can provide images of wide coverage in day, night, and all-weather conditions. However wideband SAR systems are known to be vulnerable to interferences from other devices operating at in-band or adjacent spectrums and this may lead to image corruptions. In this paper, a SAR point target simulator is developed that provides performance analysis on image distortion caused by interferences from other devices. Interference signals are generated based on the experimental data observed from acquired SAR raw data. Simulation results include typical SAR performance measures such as spatial resolution, peak to sidelobe ratio and integrated sidelobe ratio. Finally, SAR target simulations are performed and shown to correspond to the image corruptions found in real SAR missions affected by RF interferences.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.4
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• pp.247-256
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• 2008

Regenerative energy generated by regenerative braking of DC traction can cause the system malfunction or damage to the rectifier, or malfunction of the power conversion device in power supply system by DC Line voltage rise in feeder line. Regenerative energy storage system using super capacitor is one of the ways to stabilize DC line voltage. In this paper, energy storage system of DC traction system using super-capacitor bank is implemented and using the field measurement data of the station N and the station S on the Line 2, the operation characteristics of line voltage caused by regenerative energy of electric trains are verified. Also, charge/discharge characteristics of super capacitor are verified as well. Thus, we can verify the operation characteristics of super-capacitor bank for regenerative energy storage system installed in DC Traction. And if we can use field measurement data of DC line voltage, we have obtained cost reduction. The stabilization of the system will be improved by measuring the operation characteristics of regenerative energy storage system in certain section operated by DC traction and predicting the capacity and lifetime of super-capacitor.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.