• Title/Summary/Keyword: Data converter

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PostScript Conversion of ODIF Data Stream (ODIF 데이터스림의 포스트스크립트 변환)

  • 홍온선;윤근종;이수연
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.11
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    • pp.1027-1036
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    • 1991
  • This paper proposes an implementation of ODIF(Open Document Interchange Format)decoder and PostScript converter. AS ODIF data stream based on IS 8613 is described according to ASN.1 notation it is necessary to decode ODIF data stream to the proper internal structure to PostScript format as proposed in order to make hard copies in good quality using LBP(Laser Beam Printer). Among several kinds of DA(Document Architecture) and DAP(Document Application Profile). PDA(Processable DA) and Core 26(Level 2 DAP) are selected for our study. An ODIF data stream submitted by ICL is used to show the conformance in the level of data stream.

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A Microcomputer-Based Data Acquisition/Control System for Engine Performance Test(I) -Automation of Engine Performance Test and Data Acquisition- (마이크로컴퓨터를 이용한 엔진성능시험(性能試驗)의 자동화(自動化)에 관한 연구(硏究)(I) -엔진성능시험(性能試驗)과 데이터수집(蒐集)의 자동화(自動化)-)

  • Ryu, K.H.;Chung, C.J.;Park, B.S.
    • Journal of Biosystems Engineering
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    • v.12 no.3
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    • pp.7-16
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    • 1987
  • This study was carried out to develop a microcomputer-based data acquisition and control system which was able to collect the data of engine performance test automatically and control the speed and load of the engine. The results of the study are summarized as follows: 1. The signal processing devices, which were able to measure cylinder pressure, coolant temperature, compositions of exhaust gas, fuel consumption, engine rpm and torque etc., were developed. The results of calibration showed that all of devices had high accuracy ranging from 0.3% to 0.69% respectively. 2. The PIA (peripheral interface adapter) for interfacing digital signal and PTM (programmable timer module) for displaying real time every 0.0408 sec were designed and developed. 3. An engine-speed control system using a stepping motor and driver was developed. The control system had the stability, and faster settling time than the manual control system. 4. The automatic control system of electrical dynamometer, which was able to control the speed and load of dynamometer, was developed with a SSD (shackleton system driver) and D/A converter. 5. The computer programs, which were able to collect and process the data of engine tests, were developed using both the machine language and BASIC.

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Implementation of 16Kpbs ADPCM by DSK50 (DSK50을 이용한 16kbps ADPCM 구현)

  • Cho, Yun-Seok;Han, Kyong-Ho
    • Proceedings of the KIEE Conference
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    • 1996.07b
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    • pp.1295-1297
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    • 1996
  • CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

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On the Development of Speed Trial Data Measurement and Processing System (속력시운전 데이터 계측 및 분석 시스템 개발)

  • Man-Cheol Han
    • Journal of the Society of Naval Architects of Korea
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    • v.31 no.2
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    • pp.22-28
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    • 1994
  • A data acquisition and processing system. using an IBM PC, an AD converter, and a printer, has been developed to monitor rapidly and significantly varying signals. The sister takes live signals and computes and displays the trend of the moving averages of the signals in real time. The system has been applied to monitor the shaft horsepower and revolution and the speed of ships for their speed trial. The reliable interpretation of the measured data using moving average can eliminate unnecessary arguments between the owner and yard on the performance of the newly built ships. Other applications of the system-inspection of engine hunting, providing data for ship maneuvering analysis, vibration data analysis, extending to the ship performance monitoring system-are also demonstrated and discussed.

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Discriminant Analysis of Marketed Liquor by a Multi-channel Taste Evaluation System

  • Kim, Nam-Soo
    • Food Science and Biotechnology
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    • v.14 no.4
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    • pp.554-557
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    • 2005
  • As a device for taste sensation, an 8-channel taste evaluation system was prepared and applied for discriminant analysis of marketed liquor. The biomimetic polymer membranes for the system were prepared through a casting procedure by employing polyvinyl chloride, bis (2-ethylhexyl)sebacate as plasticizer and electroactive materials such as valinomycin in the ratio of 33:66:1, and were separately attached over the sensitive area of ion-selective electrodes to construct the corresponding taste sensor array. The sensor array in conjunction with a double junction reference electrode was connected to a high-input impedance amplifier and the amplified sensor signals were interfaced to a personal computer via an A/D converter. When the signal data from the sensor array for 3 groups of marketed liquor like Maesilju, Soju and beer were analyzed by principal component analysis after normalization, it was observed that the 1st, 2nd and 3rd principal component were responsible for most of the total data variance, and the analyzed liquor samples were discriminated well in 2 dimensional principal component planes composed of the 1st-2nd and the 1st-3rd principal component.

The Biological Data Converter based on BSML for Sharing Information (정보 공유를 위한 BSML 기반의 생물학 데이터 변환기)

  • 김영억;정광수;정영진;차효성;류근호
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10b
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    • pp.37-39
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    • 2004
  • 현재 생물학 연구실에서 시퀀싱 실험을 통해 생성되거나 또는 공개용 생물 데이터베이스로부터 획득된 유전체 및 단백질 정보는 각각 이질적인 데이터형식을 사용하고 있다. 이 때문에, 생물정보를 분석하여 상호간의 정보를 효율적으로 사용하기 위해서는 공통된 형식의 데이터 표준화작업이 필수적이다. 그리고 이러한 이질적 데이터 형식에 대한 표준화 연구의 미비로 인하여 플랫 파일간의 정보공유에 어려움을 겪고 있다. 따라서, 이 논문에서는 다양한 유전체 및 단백질 정보를 관리.공유하기 위해 이질적인 포맷간의 맵핑 과정을 통하여 BSML(Bioinformatic Sequence Markup Language) 형태로 변환하고, 이를 객체관계형 데이터베이스(Object Relational DataBase)에 저장하는 시스템을 개발하였다. 그리고, 개발된 시스템은 생물정보 데이터의 표준화를 위해 개발된 XML(Extend Markup Language) 기반의 BSML을 이용함으로써 효율적으로 생물학 데이터들 간의 정보를 공유할 수 있으며, 개인 생물학 데이터베이스 구축이나 다양한 생물학적 데이터를 통합 관리하는 시스템에서 유용하게 쓰일 수 있다.

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Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop

  • Song, Jae-Ho;Yoo, Tae-Whan;Ko, Jeong-Hoon;Park, Chang-Soo;Kim, Jae-Keun
    • ETRI Journal
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    • v.21 no.3
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    • pp.1-5
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    • 1999
  • A clock and data recovery circuit with a phase-locked loop for 10 Gb/s optical transmission system was realized in a hybrid IC form. The quadri-correlation architecture is used for frequency-and phase-locked loop. A NRZ-to-PRZ converter and a 360 degree analogue phase shifter are included in the circuit. The jitter characteristics satisfy the recommendations of ITU-T. The capture range of 150 MHz and input voltage sensitivity of 100 mVp-p were showed. The temperature compensation characteristics were tested for the operating temperature from -10 to $60^{\circ}C$ and showed no increase of error. This circuit was adopted for the 10 Gb/s transmission system through a normal single-mode fiber with the length of 400 km and operated successfully.

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On-Line Induction of Fermentation with recombinant cells: Optimization and Data Acquision

  • 이철균;최차용
    • Proceedings of the Korean Society for Applied Microbiology Conference
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    • 1986.12a
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    • pp.514.3-515
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    • 1986
  • λP$_{L}$ promoter와 Infiuenza virus의 NS1 Structural gene이 있는 pASl EH801 plasmid를 E. coli host N5' 과 AR120에 각각 transformation하여 온도와 nalidixic acid로 각각 induction 하여 보았다 N5151의 경우, O.D.600 1.2에서 42$^{\circ}C$로 induction하였을 때 maximum productivity를 보였으며 AR120의 경우는 O. D. 600 1.2, 37$^{\circ}C$, 40$\mu\textrm{g}$ nalidixic acid/$m\ell$ induction 하였을 때 maximum yield를 보여주었다. 이때 pH, DO, temperature, $O_2$%, $CO_2$%를 A/D converter통해 computer에 연결시켜 data acquision을 한 결과, 접종 후 ON-line induction이 가능함을 알 수 있었다.

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A Microcomputer-Based Control System for Green House (I) -Water Management- (시설원예(施設園藝)에 있어서 재배관리(栽培管理)의 자동화(自動化) 시스템에 관(關)한 연구(硏究) (I) -물관리 자동화(自動化)-)

  • Lee, K.M.;Park, K.S.
    • Journal of Biosystems Engineering
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    • v.11 no.1
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    • pp.31-36
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    • 1986
  • As a part of study on automatic control system for green houses, an automatic irrigation system was developed by using microcomputer. For the study, gypsum block was used as a sensing device of soil moisture and its data was designed to transfer to microcomputer through A/D converter. Also, software which be able to control the irrigation time and flow rate by the solenoid valve was developed. This system was tested by using practical data and the following results were summarized. 1. Since the gypsum was very accurate in addition with chiep and easy to manufacture, it turned out to be a very good device to detect the soil moisture in this system. 2. Also, solenoid valve was very excellent device for controlling the water flow rate since its control error is less then 1% when the irrigation time is over 100 seconds.

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An Implementation of Network Processor Protocol Converter and flow Control using FPGA (FPGA를 이용한 Network Processor용 Protocol 변환장치의 구현 및 흐름제어)

  • Bang, Jin-Min;Cho, Jun-Dong;Kim, Austin S.
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.397-400
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    • 2006
  • Recent trend on high speed packet processing for providing multiple internet services is to use network processor instead of being implemented by legacy ASIC or FPGA. Most frequently used network processor interface is the SPI4.2. This paper address the data-rate conversion interface device between SPI4.2 and SPI3/CSIX, implemented using XILINX XC2VP40 FPGA. Furthermore, we address the methodology and necessity of flow control occurred due to the data rate difference between 10Gbps and 3.2 Gbps.

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