• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.387-398
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• 2006

In this paper, we propose a new page allocation scheme for flash memory file system. The proposed scheme allocates pages by exploiting the concept of Purity, which is defined as the fraction of blocks where valid Pages and invalid Pages are coexisted. The Pity determines the cost of block cleaning, that is, the portion of pages to be copied and blocks to be erased for block cleaning. To enhance the purity, the scheme classifies hot-modified data and cold-modified data and allocates them into different blocks. The hot/cold classification is based on both static properties such as attribute of data and dynamic properties such as the frequency of modifications. We have implemented the proposed scheme in YAFFS and evaluated its performance on the embedded board equipped with 400MHz XScale CPU, 64MB SDRAM, and 64MB NAND flash memory. Performance measurements have shown that the proposed scheme can reduce block cleaning time by up to 15.4 seconds with an average of 7.8 seconds compared to the typical YAFFS. Also, the enhancement becomes bigger as the utilization of flash memory increases.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.6
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• pp.422-426
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• 2007

Personal mobile devices equipped with non-volatile storage such as MP3 player, PMP, cellular phone, and USB memory require safety for the stored data on the devices. One of the safety requirements is secure deletion, which is removing stored data completely so that the data can not be restored illegally. In this paper, we study how to design the secure deletion on Flash memory, commonly used as storage media for mobile devices. We consider two possible secure deletion policy, named zero-overwrite and garbage-collection respectively, and analyze how each policy affects the performance of Flash memory file systems. Then, we propose an adaptive file deletion scheme that exploits the merits of the two possible policies. Specifically, the proposed scheme applies the zero-overwrite policy for small files, whereas it employs the garbage-collection policy for large files. Real implementation experiments show that the scheme is not only secure but also efficient.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.101-121
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• 2010

This paper presents an intelligent prefetching technique that significantly improves performance of hybrid fash-disk storage, a combination of flash memory and hard disk. Since flash memory embedded in a hybrid device is much faster than hard disk in terms of I/O operations, it can be utilized as a 'cache' space to improve system performance. The basic strategy for prefetching is to utilize sequential pattern mining, with which we can extract the access patterns of objects from historical access sequences. We use two techniques for enhancing the performance of hybrid storage with prefetching. One of them is to modify a FAST algorithm for mapping the flash memory. The other is to extend the unit of prefetching to a block level as well as a file level for effectively utilizing flash memory space. For evaluating the proposed technique, we perform the experiments using the synthetic data and real UCC data, and prove the usability of our technique.

• Spatial Information Research
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• v.20 no.5
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• pp.67-76
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• 2012

Recently the mobile DBMS (Database Management System) is popular to store and manage large data in a mobile device. Especially, the research and development about mobile storage structure and querying method for navigation map data in a mobile device have been performed. The performance of the mobile DBMS in which random data accesses are most queries if the NAND flash memory is used as storage media of the DBMS is degraded. The reason is that the performance of flash memory is good in writing sequentially but bad in writing randomly as the features of the NAND flash memory. So, new storage structure and querying policies of the mobile DBMS are needed in the mobile DBMS in which a flash memory is used as storage media. In this paper, we have studied the policy of the database page management to enhance the performance of the frequent random update and applied this policy to the navigation-specialized mobile DBMS which supports incremental map update. And also we have evaluated the performance of this policy by experiments.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.1-12
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• 1999

In this paper, we designed an embedded processor with 128Kbytes EPROM and 4Kbytes SRAM based on GMS30C2132 which RISC processor with DSP functions. And a new architecture of bus sharing to control the embedded memory and external memory unit i proposed aiming at one-cycle access between memories and CPU. For embedded 128Kbytes EPROM, we designed the new expansion interface for data size at data ordering with memory organization and the efficient interface for test. The embedded SRAM supports an extended stack area high speed DSP operation, instruction cache and variable data-length control which is accessed with 4K modulo addressing schemes. The proposed new architecture and circuits reduced the memory access cycle time from 40ns and improved operation speed 2-times for program benchmark test. The chip is occupied $108.68mm^2$ using $0.6{\mu}m$ CMOS technology.

• KIPS Transactions on Computer and Communication Systems
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• v.1 no.1
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• pp.11-20
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• 2012

Stream data shows a sequence of values changing continuously over time. Due to the nature of stream data, its trend is continuously changing according to various time intervals. Therefore the prediction of stream data must be carried out simultaneously with respect to multiple intervals, i.e. Continuous Multiple Prediction(CMP). In this paper, we propose a Continuous Integrated Hierarchical Temporal Memory (CIHTM) network for CMP based on the Hierarchical Temporal Memory (HTM) model which is a neocortex leraning algorithm. To develop the CIHTM network, we created three kinds of new modules: Shift Vector Senor, Spatio-Temporal Classifier and Multiple Integrator. And also we developed learning and inferencing algorithm of CIHTM network.

• Journal of KIISE
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• v.42 no.4
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• pp.427-433
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• 2015

The rapid advancement of computing technology has triggered the need for fast data I/O processing and high-performance storage technology. Next generation memory technology, which we refer to as new memory, is anticipated to be used for high-performance storage as they have excellent characteristics as a storage device with non-volatility and latency close to DRAM. This research proposes NTL (New memory Translation layer) as a technology to make use of new memory as storage. With the addition of NTL, conventional I/O is served with existing mature disk-based file systems providing compatibility, while new memory I/O is serviced through the NTL to take advantage of the byte-addressability feature of new memory. In this paper, we describe the design of NTL and provide experiment measurement results that show that our design will bring performance benefits.

• The Korean Journal of Rehabilitation Nursing
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• v.5 no.2
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• pp.205-216
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• 2002

This quasi-experimental study was done to test the effects of meta-memory enhancing program for elderly women. Data were collected 12 to 30, August 2002 from 34elderly women over 65 years living in Busan city. Subjects were 15 of experimental group and 19 of control group. The metamemory enhancing program was developed by five sessions composing of 1.5-2.0 hours one session. In experiment group, this program was performed for three weeks, twice per week. The degrees of four memory performance tasks were measured using instrument of Elderly Verbal Learning Test(Choi Kyung Mi, 1988) and Face Recognition Instrument(Min Hye Sook, 1999) and the metamemory were measured using MIA questionnaire(Dixon et al., 1988). Research results are as following. 1. After participating in five times memory training programs, experimental group has the significant increase of metamemory in comparison with control group.(t=59.58, p< 0.0001). In particular, the concepts of strategy(t=20.44, p< 0.0001), achievement (t=21.94, p< 0.0001), and locus degree (t=59.58, p< 0.0001) among sub-concepts of the metamemory are increasing significantly. 2. After participating in five time memory training programs, the degree of immediate word recall(t=17.25, p< 0.0001) and face recognition(t=16.69, p< 0.0001) among four memory tasks in experimental group are increasing significantly compared with those measures of control group. Considering this results, this metamemory enhancing program was found as an effective nursing program for metamemory improvement of elderly women's memory.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.497-508
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• 2008

Mobile Multimedia File System, MNFS, is a file system which extensively exploits NAND FLASH Memory, Since general Flash file systems does not precisely meet the criteria of mobile devices such as MP3 Player, PMP, Digital Camcorder, MNFS is designed to guarantee the optimal performance of FLASH Memory file system. Among many features MNFS provides, there are three distinguishable characteristics. MNFS guarantees, first, constant response time in sequential write requests of the file system, second, fast file system mounting time, and lastly least memory footprint. MNFS implements four schemes to provide such features, Hybrid mapping scheme to map file system metadata and user data, manipulation of user data allocation to fit allocation unit of file data into allocation unit of NAND FLASH Memory, iBAT (in core only Block Allocation Table) to minimize the metadata, and bottom-up representation of directory. Prototype implementation of MNFS was tested and measured its performance on ARM9 processor and 1Gbit NAND FLASH Memory environment. Its performance was compared with YAFFS, NAND FLASH File system, and FAT file system which use FTL. This enables to observe constant request time for sequential write request. It shows 30 times faster mounting time to YAFFS, and reduces 95% of HEAP memory consumption compared to YAFFS.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.149-156
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• 2012

Support vector machines (SVMs) are well known for their pattern recognition capability, but proper care should be taken to alleviate their inherent implementation cost resulting from high computational intensity and memory requirement, especially in embedded systems where only limited resources are available. Since the memory requirement determined by the dimensionality and the number of support vectors is generally too high for a cache in embedded systems to accomodate, frequent accesses to the main memory occur inevitably whenever the cache is not able to provide requested data to the processor. These frequent accesses to the main memory result in overall performance degradation and increased energy consumption because a memory access typically takes longer and consumes more energy than a cache access or a register access. In this paper, we propose a technique that reduces the number of main memory accesses by optimizing the data access pattern of the SVM-based classifier in such a way that the temporal locality of the accesses increases, fully utilizing data loaded into the processor chip. With experiments, we confirm the enhancement made by the proposed technique in terms of the number of memory accesses, overall execution time, and energy consumption.