• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제15권1호
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• pp.1-13
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• 2009

플래시 메모리는 크기가 작고, 적은 전력을 사용하며 충격에 강하기 때문에 MP3 플레이어, 핸드폰, 디지털 카메라와 같은 휴대용 기기에서 저장장치로 널리 사용되고 있다. 플래시 메모리의 많은 장점 때문에 개인용 컴퓨터 및 노트북에서 사용되는 저장장치인 하드디스크를 플래시 메모리로 대체하고자 하는 연구도 진행되고 있다. 플래시 메모리는 덮어쓰기가 허용되지 않으며 읽기/쓰기의 기본 단위와 삭제의 기본 단위가 다르기 때문에 FTL(Flash Translation Layer)라는 플래시 변환 계층을 사용한다. 최근에는 기존의 플래시 메모리와 다른 물리구조와 특성을 갖는 대블록 플래시 메모리가 등장하여 기존의 FTL을 그대로 사용하게 되면 플래시 메모리를 효율적으로 사용할 수 없다. 본 논문에서는 기존의 FTL 중 가장 좋은 성능을 내는 FAST(Fully Associative Sector Translation)을 기반으로 데이타블록 내에서 페이지단위 사상을 적용하여 대블록 플래시 메모리의 특성에 맞는 FTL 기법을 제안한다.

• 한국전산구조공학회:학술대회논문집
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• 한국전산구조공학회 2004년도 봄 학술발표회 논문집
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• pp.389-395
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• 2004

We consider the interface between the parallel distributed memory multifrontal solver and the finite element method. We give in detail the requirement and the data structure of parallel FEM interface which includes the element data and the node array. The full procedures of solving a large scale structural problem are assumed to have pre-post processors, of which algorithm is not considered in this paper. The main advantage of implementing the parallel FEM interface is shown up in the case that we use a distributed memory system with a large number of processors to solve a very large scale problem. The memory efficiency and the performance effect are examined by analyzing some examples on the Pegasus cluster system.

• International Journal of Advanced Culture Technology
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• 제5권4호
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• pp.57-62
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• 2017

In this paper, we applied long short term memory(LSTM) for classifying political polarity in cyber public sphere. The data collected from the cyber public sphere is transformed into word corpus data through word embedding. Based on this word corpus data, we train recurrent neural network (RNN) which is connected by LSTM's. Softmax function is applied at the output of the RNN. We conducted our proposed system to obtain experimental results, and we will enhance our proposed system by refining LSTM in our system.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권4호
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• pp.180-186
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• 2002

This paper describes on the development of power detection system with one-chip microcontroller. The designed system is composed of power detection circuits and analyzing software. The system detects, 3-phases voltage, 3-phases current, external temperature, leakage current and stores in flash memory. AT89C52 was used as CPU and AM29F040B was used as memory to store the data. The analysis saftware was developed to detect the cause of the electrical fire incidents. With a data-compression technology, the data can be stored for the 43.5 days in a normal state, four hours and fifteen minutes in emergency state.

• 전자통신동향분석
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• 제13권3호통권51호
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• pp.61-70
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• 1998

The obvious way to make a computer system more powerful is to make the processor as fast as possible. Furthermore, adopting a large number of such fast processors would be the next step. This multiprocessor system could be useful only if it distributes workload uniformly and if its processors are fully utilized. To achieve a higher processor utilization, memory access latency must be reduced as much as possible and even more the remaining latency must be hidden. The actual latency can be reduced by using fast logic and the effective latency can be reduced by using cache. This article discusses what the memory latency problem is, how serious it is by presenting analytical and simulation results, and existing techniques for coping with it; such as write-buffer, relaxed consistency model, multi-threading, data locality optimization, data forwarding, and data prefetching.

• 대한수학회보
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• 제53권5호
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• pp.1439-1446
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• 2016

The execution complexities of the major time memory data tradeoff methods are analyzed in this paper. The multi-target tradeoffs covered are the classical Hellman, distinguished point, and fuzzy rainbow methods, both in their non-perfect and perfect table versions for the latter two methods. We show that their computational complexities are identical to those of the corresponding single-target methods executed under certain matching parameters and conclude that the perfect table fuzzy rainbow tradeoff method is most preferable.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.477-479
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• 2018

본 연구는 인공신경망의 한 종류인 LSTM(Long Short-Term Memory) 기법을 활용하기 위하여 진행하였다. UTD(University of Texas at Dallas)가 공개한 27종 동작 데이터 중 3축 가속도 및 각속도 데이터를 기본 LSTM 및 Deep Residual Bidir-LSTM 기법에 적용하여 행동을 분류해 보았다.

• 대한전기학회논문지
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• 제35권8호
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• pp.309-315
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• 1986

We proposed a preliminary Data Flow Machine Model(DNL1) operating on the basis of Node Label. In this model, all the PMs(Processing Modules) were synchronized with the content of LC(Level Counter) and were not implemented dy the processing cability on conditional nodes. This paper presents an architecture of a concurrent multiprocessor system which was developed from DNL1 with two additional types of memories, CF(Control Flag) and ETF (Enabled Token Flag). The CF memory holds the control condition flag ('1' or '0') to be referenced to when a node is fired and the ETF represents the firability of a certain node. Firable nodes are fetched to the PU(Processing Unit) and processed. This Data Flow system can be extended hierarchically by a network of simple modules. The principle working elements of the machine are a set of PMs, each of which performs the execution of the data flow procedures held in a local memory, NTM(Node Token Memory) within the PM.

• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 한국군사과학기술학회지
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• 제14권5호
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• pp.842-849
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• 2011

The transponder simulator designed to simulate the transponder of military satellite communication systems in the geostationary orbit is required to have time delay function, because of 250 ms delay time, when a radio wave transmits the distance of 36,000 km in free space. But, it is very difficult to develop 250 ms time delay device in the transponder simulator of 100 MHz bandwidth, due to unstable operation of FPGA, loss of memory data for the high speed rate signal processing. Up to date, bandwidth of the time delay device is limited to 45 MHz bandwidth. To solve this problem, we propose the new time delay techniques up to 100 MHz bandwidth without data loss. Proposed techniques are the low speed down scaling and high speed up scaling methods to read and write the external memory, and the matrix structure design of FPGA memory to treat data as high speed rate. We developed the satellite link simulator in 100 MHz bandwidth using the proposed new time delay techniques, implemented to the transponder simulator and verified the function of 265 ms time delay device in 100 MHz bandwidth.