• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.9
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• pp.825-832
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• 2016

This paper describes the development of a data bus analyzer for use in avionics systems integration test. The data bus analyzer is equipped with MIL-STD-1553B, CAN and Ethernet interface cards which is incorporated in a majority of the avionics systems to accommodate a variety of interfaces. It has an individual hardware for a capture engine and a analyzing engine in order to perform the collection and the analysis of the bus data at the same time efficiently. It provides a data display function of the grid, 2-dimensional and 3-dimensional form to increase the data analysis efficiency. Verification of the data bus analyzer was carried out module unit testing and inter-module integration testing on the basis of the test procedures. Verification of interlocking requirement and usefulness of developed equipment was confirmed through an integration test result performed on a system integration laboratory of aircraft which is an actual testing environment.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1111-1115
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• 1987

This paper describes of VME-BSA which is a tool for the development, mainternance and repair. In micro/mini computer system using VMEbus as a backplane bus, VME-BSA has some good facilities such as acquiring, storing and analyzering the information (address, data, etc.) on VMEbus according to the various condition which is set by users, and therefore it is easy to isolate and find many complete errors on bus.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1936-1945
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• 2008

In Korea, TCN has applied to the Korean High-speed Train (HSR350X) through G7 High-speed Train development project. TCN is the most suitable international standard communication network for distributed control systems that is adopted for high-speed of vehicle, safety and flexibility. TCN is the network exclusively for the high-speed train and electrical trains. This TCN satisfies the network standards. The network standards are real time communication, fault tolerance design, integrated data system, resistance of environment, automated recognition for modification of vehicle formation and maintenance. The purpose of this research is applying the development of WTB analyzer which is part of communication network system TCN, to check the communication of high-speed trains and electrical trains.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.9
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• pp.1332-1347
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• 1993

Existing instruments are composed independently according to their function and user constructed instrumentation system with those instruments. But in the late 1980s VXI bus enables to construct instrumentation system with various modular type instruments. For an VXI bus system with the word serial protocol, an increase of data size can degrade the system performance. In this paper shared memory protocol is proposed to overcome performance degradation. The shared memory protocol is analyzed using the GSPN and compared with that of the word serial protocol. It is shown that the shared memory protocol has a better performance than the word serial protocol. The VXI bus message based-system with the proposed shared memory protocol is constructed and experimented with signal generating device and FFT analyzing device. Up to 80 KHz input signal the result of FFT analysis is accurate and that result is agree with that of conventional FFT analyzer. In signal generating experiment from 100 KHz to 1.1 GHz sine wave is generated.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.