• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.75-82
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• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.192-195
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• 2002

About 90% of Thai-style addresses have similar features; e.g. the beginning of each address line is diagonal. In this paper, we propose a method for locating destination address block (DAB) on Thai envelopes based on features of Thai-style addresses. Firstly, we decompose image into smaller blocks and remove all blocks not meeting criteria. Secondly, we search for the DAB candidates. Lastly, heuristic rules and typical features are applied to identify the destination address block. Experimental results using 2,700 envelopes of handwritten and machine printed Thai envelopes show a successful address extraction rate of 91%.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1650-1660
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• 2016

This paper proposes a compensator to eliminate the DC bias of inductor current. This method utilizes an average-current sensing technique to detect the DC bias of inductor current. A small signal model of the DC bias compensation loop is derived. It is shown that the DC bias has a one-pole relationship with the duty cycle of the left side leading lag. By considering the pole produced by the dual active bridge (DAB) converter and the pole produced by the average-current sensing module, a one-pole-one-zero digital compensation method is given. By using this method, the DC bias is eliminated, and the stability of the compensation loop is ensured. The performance of the proposed compensator is verified with a 1.2-kW DAB converter prototype.

• ETRI Journal
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• v.26 no.2
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• pp.112-121
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• 2004

Digital Multimedia Broadcasting (DMB) is an upcoming standard in Korea used to provide mobile multimedia broadcasting service based on the Eureka-147 Digital Audio Broadcasting (DAB) system. The current dominant multimedia coding standard, MPEG-4, is foreseen to play an important role in forthcoming DMB services. However, the current approaches for transporting MPEG-4 content over DMB networks are not optimized. To address this issue we propose a novel MPEG-4 stream multiplexer, called M4SMux, which provides better stream multiplexing and delivery over DMB networks. M4SMux features an MPEG-4 elementary-stream interleaving mechanism that reduces the multiplexing overhead and a multiplex configuration mechanism that utilizes M4SLinkTable for easy content access. In addition, we propose an error correction method which enhances transport efficiency.

• ETRI Journal
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• v.33 no.6
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• pp.969-972
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• 2011

This letter presents a CMOS RF front-end operating in a subthreshold region for low-power Band-III mobile TV applications. The performance and feasibility of the RF front-end are verified by integrating with a low-IF RF tuner fabricated in a 0.13-${\mu}m$ CMOS technology. The RF front-end achieves the measured noise figure of 4.4 dB and a wide gain control range of 68.7 dB with a maximum gain of 54.7 dB. The power consumption of the RF front-end is 13.8 mW from a 1.2 V supply.

• Journal of Digital Convergence
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• v.11 no.2
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• pp.287-297
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• 2013

In this paper, we propose an efficient variable-length radix-8/4/2 FFT architecture for OFDM systems. The FFT processor is based on radix-8 FFT algorithm and also supports radix-4 or radix-2 FFT computation. We are using efficient "In-place" memory access method to maintain conflict-free data access and minimize memory size. Also we replace a very large lookup table with a twiddle factor generator which consumes less area then a ROM-based lookup table. The proposed FFT processor performs variable-length FFT including 64, 256, 512, 1024, 2048, 4096 and 8192 points which cover all the required FFT lengths used in 802.11a, 802.16a, DAB, DVB-T, VDSL and ADSL.

• Journal of IKEEE
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• v.23 no.3
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• pp.994-1002
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• 2019

In this paper, we propose the development of a power conversion system for electric power take-off (e-PTO) of agricultural electric vehicles. Most e-PTOs use commercial power $220V_{AC}$. A bidirectional power conversion system having a two-stage structure consisting of a DC-DC converter and a DC-AC inverter for supplying a high output voltage using a low battery voltage of an agricultural electric vehicle is suitable. we propose a power conversion system consisting of the one-stage dual active bridge (DAB) converter and the two-stage bidirectional full bridge inverter. In addition, we propose a soft start algorithm for reducing the inrush current generated by the link capacitor charging during the initial operation. A 3kW prototype system and its corresponding algorithms have been implemented to verify its effectiveness through experiments.

• Proceedings of the Korean Society of Crop Science Conference
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• 2017.06a
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• pp.118-118
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• 2017

A high-resolution physical map targeting a cluster of yield-related QTLs on the long arm of rice chromosome 9 was constructed across a 35.5kb region containing the six predicted genes including the probable ascorbate peroxidase (OsApx). The $BC_3F_6$ near isogenic lines (NILs) were derived from a cross between the Oryza sativa Hwaseong and O. rufipogon. The plant height and length of internodes were compared between Hwaseong and NILs. There were significant differences in plant height between Hwaseong and NILs. The NILs internodes were longer than Hwaseong, showing dramatic elongation in the first and fourth internodes; thereby, leading to increased plant height. The antioxidant activity of Hwaseong and NILs was also analyzed by 3,3-diaminobenzidine (DAB) staining and 2,2-diphenyl-1-picrylhydrazyl (DPPH) assay. In order to understand whether or not OsApx gene is important in scavenging $H_2O_2$ in rice, DAB staining was used. Intense dark-brown coloration was observed in Hwaseong than NILs. In addition, DPPH scavenging ability of Hwaseong showed lower value than NILs. These results indicated that the internode elongation and antioxidant activity might possibly be controlled by OsApx. To know the causative relationship of the gene and phenotype, we will further analyze the gene expression and use it for functional studies by complementation transgenic approach.