• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.1C
• /
• pp.12-18
• /
• 2008

This paper This paper proposes a new inverse-quantization(IQ) table interpolation algorithm, specialized Digital Signal Processor(DSP) instructions and hardware architecture for digital audio codecs. Non-linear inverse quantization algorithm is representatively used in both MPEG-1 Layer-3 and MPEG-2/4 Advanced Audio Coding(AAC). The proposed instructions are optimized for the non-linear inverse quantization. The proposed algorithm can minimize operational complexity which reduces total computational load. Performance comparisons show a significant improvement of average error. The proposed instructions and hardware architecture can reduce 20% of the instruction counts and minimize computational loads of IQ algorithms effectively compared with existing IQ table interpolation algorithms. Proposed algorithm can implement commercial DSPs.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
• /
• 2003.05a
• /
• pp.319-323
• /
• 2003

In this paper, we propose a hybrid transceiver for underwater acoustic communication, which allows the system to reduce complexity and increase robustness in time variant underwater channel environments. It is designed in the digital domain except for amplifiers and implemented by using a multiple digital signal processors (DSPs) system. The digital modulation technique is quadrature phase shift keying (QPSK) and frame synchronization is an energy (non-coherent) detection scheme based on the quadrature receiver structure. DSP implementation is based on block data parallel architecture (BDPA). We shaw experimental results in th? underwater anechoic basin at KRISO. The results indicate that the frame synchronization is performed without PLL. Also, we shaw that the adaptive equalizer can compensate frame synchronization error and the correction capability is dependent on the length of equalizer.

• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.563-566
• /
• 2003

We have designed the power control unit which belongs to the power cabinet and controls the power supplied to Control Rod Drive Mechanism(CRDM) as a digital system based on Digital Signal Processor(DSP). The power control unit dualized as the form of Master/Slave has had its increased reality. The Central Process Unit(CPU) board of a power control unit possesses two Digital Signal Processors(DSPs) of the control DSP for performing the tasks of power control and system monitoring and the communication of the Control DSP and the Communication DSP. To accomplish the functions requested in the power control unit effectively, we have installed Field Programmable Gate Arrays(FPGAS) on the CPU board and have FPGAs perform the memory mapping, the generation of each chip selection signal, the giving and receiving of the signals between the power controllers dualized, the fault detection and the generation of the firing signals.

• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.280-286
• /
• 2022

This paper presents implementation of rapid control prototype (RCP) for permanent magnet synchronous machines (PMSMs) using a digital signal processor (DSP) and the PLECS software. By utilization of auto code generation function in the PLECS, a current vector control algorithm for a PMSM drive system using a DSP as a control processor can be developed more efficiently. In this paper, a background of a model based design (MBD) and real time control are reviewed. Also, commercial RCP products compatible with DSP boards are introduced. At the end of the paper, experimental implementation of RCP for a PMSM drive is presented.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.16 no.8
• /
• pp.2816-2830
• /
• 2022

Number Theoretic Transform (NTT) is a method to design efficient multiplier for large integer multiplication, which is widely used in cryptography and scientific computation. On top of that, it has also received wide attention from the research community to design efficient hardware architecture for large size RSA, fully homomorphic encryption, and lattice-based cryptography. Existing NTT hardware architecture reported in the literature are mainly designed based on radix-2 NTT, due to its small area consumption. However, NTT with larger radix (e.g., radix-4) may achieve faster speed performance in the expense of larger hardware resources. In this paper, we present the performance evaluation on NTT architecture in terms of hardware resource consumption and the latency, based on the proposed radix-2 and radix-4 technique. Our experimental results show that the 16-point radix-4 architecture is 2× faster than radix-2 architecture in expense of approximately 4× additional hardware. The proposed architecture can be extended to support the large integer multiplication in cryptography applications (e.g., RSA). The experimental results show that the proposed 3072-bit multiplier outperformed the best 3k-multiplier from Chen et al. [16] by 3.06%, but it also costs about 40% more LUTs and 77.8% more DSPs resources.

• Journal of the Korean Society for Precision Engineering
• /
• v.13 no.10
• /
• pp.94-104
• /
• 1996

This paper presents a new approach to the design of adaptive control system using DSPs(TMS320C31) for robotic manpulators to achieve accurate trajectory tracking by the joint angles Digital signal processors are used in implementing real time adaptive control algorithms to provide an enhanced motion control for robotic manipulators. In the proposed contorl scheme, adaptation laws are derived from the improved Lyapunov second stability analysis method based on the adaptive model reference control theory. The adaptive controller consists of an adaptive feedforward controller, feedback controller, and PID type time varying auxillary control elements. The proposed adaptive control scheme is simple in structure, fast in computation, and suitable for implementation of real-time control. Morever, this scheme does not require an accurate dynamic modeling nor values of manpipulator parameters and payload. Performance of the adaptive controller is illustated by simulation and experimental results for a SCARA robot.

• Journal of Sensor Science and Technology
• /
• v.32 no.4
• /
• pp.246-251
• /
• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.2
• /
• pp.72-81
• /
• 2002

A new high-performance DSP architecture is proposed, which behaves as a coprocessor of a 32bit microcontroller. Because the proposed DSP architecture is a dual MAC(Multiply and Accumulate) DSP architecture, it can process efficiently a number of SOP(sum of product) operations used in many DSP applications. In order to efficiently perform other operations such as pure additions without any restriction, a MAC is composed of a multiplier and a ALU placed in parallel. In addition, it is a 3-way superscalar architecture, which can issue 3 instructions at a time. The benchmark results with 3 thor dual MAC DSPs show that the proposed DSP has the best performance. Futhermore, it is proven that the proposed DSP is more efficient in memory usage, although the performance is comparable in some algorithms such as Viterbi decoding and FFT butterfly.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.6
• /
• pp.36-45
• /
• 2005

This paper addresses the application of motor current spectral analysis for the detection of rolling-element bearing damage in induction machines. We set the experimental test bed. They is composed of the normal condition bearing system, the abnormal rolling-element bearing system of 2 type induction motors with shaft deflection system by external force and a hole drilled through the outer race of the shaft end bearing of the four pole test motor. We have developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module is checking stator current The effects on the stator current spectrum are described and related frequencies are also determined. This is an important result in the formulation of a fault detection scheme that monitors the stator currents. We utilized the FFT(Fast Fourier Transform), Wavelet analysis and averaging signal pattern by inner product tool to analyze stator current components. Especially, the analyzed results by inner product clearly illustrate that the stator signature analysis can be used to identify the presence of a bearing fault.

• The Journal of the Acoustical Society of Korea
• /
• v.23 no.2
• /
• pp.117-124
• /
• 2004

In this paper, we have been implemented the QPSK-based underwater transmission systems using DSP in order to transmit the underwater image data. We have adopted a BDPA (Block Data Parallel Architecture) to control multiple DSPs used in the transmitter and receiver in order to transmit the image data in real-time. We also have developed GUI software in order to drive and to debug the implemanted system in real-time. We have executed open sea tests in order to analyze the performance of the implemented system at East Sea near Kosung in Kangwon-Do. As a result of these experiments, it has been demonstrated that 10 kbps image data can be received without errors at 30m and 80m depth points, while the distance between the transmitter and the receiver is up to 20m.