• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.12C
• /
• pp.727-737
• /
• 2011

This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of $640{\times}480$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.62-71
• /
• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.

• 전자공학회논문지 IE
• /
• v.47 no.4
• /
• pp.18-27
• /
• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.11
• /
• pp.74-84
• /
• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.11
• /
• pp.31-38
• /
• 1998

This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

• Journal of the Institute of Convergence Signal Processing
• /
• v.14 no.1
• /
• pp.62-69
• /
• 2013

This paper proposes real-time video transmission system by the car-mounted cameras based on MOST Network. Existing vehicles transmit videos by connecting the car-mounted cameras in the form of analog. However, the increase in the number of car-mounted cameras leads to development of the network to connect the cameras. In this paper, DSP is applied to process MPEG 2 encoding/decoding for real-time video transmission in a short period of time. MediaLB is employed to transfer data stream between DSP and MOST network controller. During this procedure, DSP cannot transport data stream directly from MediaLB. Therefore, FPGA is used to deliver data stream transmitting MediaLB to DSP. MediaLB is designed to streamline hardware/software application development for MOST Network and to support all MOST Network data transportation methods. As seen in this paper, the test results verify that real-time video transmission using proposed system operates in a normal matter.

• MALSORI
• /
• no.52
• /
• pp.121-132
• /
• 2004

This paper is aiming at real-time implementation of adaptive noise cancellation system using DSP processor. ACHARF algorithm, which guarantees stability and fast convergence by adaptive compensator, is used on this DSP system. For the experiments, TLV320AIC23 stereo CODEC of TI Inc. is used with TMS320C6413 DSP processor. Signals of primary input and reference input are obtained by two microphones. The primary input is the voice plus noise signal and the reference input is white noise or real noise. The experimental results show that ANC system using DSP processor with ACHARF is verified to be an effective speech enhancement method for various speech processing units.

• 제어로봇시스템학회:학술대회논문집
• /
• 1997.10a
• /
• pp.480-483
• /
• 1997

A fossil power plant can be modeled by a lot of algebraic equations and differential equations. When we simulate a large, complicated fossil power plant by a computer such as workstation or PC, it takes much time until overall equations are completely calculated. Therefore, new processing systems which have high computing speed is ultimately needed to develope real-time simulators. Vital points of real-time simulators are accuracy, computing speed, and deadline observing. In this paper, we present a enhanced strategy in which we can provide powerful computing power by parallel processing of DSP processors with communication links. We designed general purpose DSP modules, and a VME interface module. Because the DSP module is designed for general purpose, we can easily expand the parallel system by just connecting new DSP modules to the system. Additionally we propose methods about downloading programs, initial data to each DSP module via VME bus, DPRAM and processing sequences about computing and updating values between DSP modules and CPU30 board when the simulator is working.

• KIPE Magazine
• /
• v.9 no.3
• /
• pp.13-17
• /
• 2004

근래에 Texas Instruments(TI)사에서 개발된 TMS3320LF240x는 고정 소숫점 방식의 16비트 DSP으로써 저가, 고성능용으로 개발된 칩이다. 이 DSP는 비교적 빠른 계산속도에 다양한 입력/출력장치를 내장하고 있으므로 DSP 장점과 마이크로제어기의 장점을 모두 가지고 있다. 특히 Flash 메모리, RAM 등 메모를 포함하여 8-16채널 이상 A/D 컨버터, Timer, 직력통신과 함께 PWM인버터/컨버터용 PWM펄스까지 출력시킬 수 있으므로, 이 DSP는 각종 전동기 구동시스템과 SUP, 능동필터 제어 등 전력전자 분야에서 적합하게 설계된 DSP로 상당히 많이 사용되고 있다. 그런데 TMS320LF240x는 고정 소숫점 방식의 16비트 DSP이므로 연산량이 많은 시스템에서는 적용하기 힘들며, 또는 저장할 데이터량이 많은 제어시스템일 경우에는 내장된 flash 및 SRAM 등 메모리 용량이 부족하는 등 사용하는데 문제가 있을 가능성이 있다.(중략)

• Proceedings of the Acoustical Society of Korea Conference
• /
• 1998.06e
• /
• pp.323-326
• /
• 1998

본 논문에서는 한국통신에서 음성인식을 이용한 전화정보 서비스의 일환으로 개발해 온 증권정보 시스템의 구조와 기능을 설명하고, 시스템을 다채널로 확장함에 있어서 시스템의 자원을 효율적으로 활용하기 위하여 적용한 방법에 대하여 기술하였다. 이 시스템에서는 음성특징을 추출하는 프로세서(DSP0)들과 단억검색을 하는 프로세서(DSP1)들이 분리되어 있으며, 이 둘 간의 개수 비율을 조절함으로써 실시간적 처리 효과를 유지하면서도 시스템의 전체 프로세서의 개수를 줄였다. DSP0와 DSP1 간의 음성 특징 데이터 전송에 있어서는 DSP0에서 발생하는 데이터를 음성이 입력되는 중에 전송할 수 있게 함으로써, DSP1에서는 DSP0과 병렬적으로 작업을 수행시킬 수 있으며, 결과적으로 시스템의 속도를 빠르게 하였다.