• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.6
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• pp.1138-1145
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• 2009

This paper presents an active and reactive power compensator for the wind power system with squirrel-cage induction generator. The output power of a wind power system changes irregularly according to the variation of wind speed. The developed system is able to continuously compensate the active and reactive power. The 3-phase inverter operates for the compensation of reactive power, while the DC/DC converter with super-capacitors operates for the compensation of active power. The operational feasibility of the proposed model was verified by simulations with PSCAD/EMTDC and the feasibility of hardware implementation was confirmed by experimental works with a scaled hardware model. The proposed compensator can be expected that developed system may be used to compensated the abrupt power variation due to sudden change of wind speed or sudden power-drop by tower effect. It can be also applied for the distributed generation and the Micro-Grid.

• Transactions of the Korean Society of Automotive Engineers
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• v.19 no.2
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• pp.72-77
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• 2011

In this paper, we propose effective diagnosis algorithm for hub bearing fault in driving vehicle using acceleration signal and wheel speed signal measured in hub bearing unit or knuckle. This algorithm consists of differential, envelope and power spectrum method. We developed diagnosis system for realizing proposed algorithm. This system consists of input device including acceleration sensor and wheel speed sensor, calculation device using Digital Signal Processor (DSP) and display device using Personal Digital Assistant (PDA). Using this diagnosis system, a driver can see hub bearing fault(flaking) from the vibration in driving vehicle. With early repairing, he can keep good ride feeling and prevent accident of vehicle resulting from hub bearing fault.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.3
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• pp.154-161
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• 2005

This paper proposes a speed-sensorless induction motor control system using a rotor speed compensation. To explain the proposed system, this paper describes an induction motor model in the synchronous reference frame for the vector control. The rotor flux is estimated by the rotor flux observer using the reduced-dimensional state estimator technique. The estimated rotor speed is directly obtained from the electrical frequency, the slip frequency, and the rotor speed compensation with the estimated q-axis rotor flux. The error of the rotor time constant is indirectly reflected in the rotor speed compensation using the compensation of the flux error angle. To precisely estimate the rotor flux, the actual value of the stator resistance, whose actual variation is reflected, is derived. An implementation of pulse-width modulation (PWM) pulses using an effective space vector modulation (SVM) is briefly mentioned. For fast calculation and improved performance of the proposed algorithm, all control functions are implemented in software using a digital signal processor (DSP) with its environmental circuits. Also, it is shown through experimental results that the proposed system gives good performance for the speed-sensorless induction motor control.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1088-1090
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• 2001

In general, Power SCR(Silicon Controlled Rectifier) is most widely used in Power Plant as well as Industrial field. It has been controlled and operated according to its own control method. Especially, in case of Power plant, it plays a major role in AVR(Automatic Voltage Regulator) or electro chlorination control circuits. Generally, they used in Analog control system at above field. But each SCR current value is different because of load unbalance or switching characteristic variations, it may cause power plant unit trip or system disorder according to SCR element burn out or bad operating condition. Therefore, in this paper a development of 3 phase current balance control unit is described, it gets over the past analog control system limit, uses DSP(Digital signal processor) had high speed response, controls SCR gate firing angle for 3 phase current balance.

• Proceedings of the KIEE Conference
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• 2006.11a
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• pp.6-8
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• 2006

변전소 자동화 시스템에서 IED(Intelligent Electronic Device)들 간의 효과적인 통신을 위해 표준프로토콜인 IEC-61850이 제시되면서 이를 구현하고 응용하기 위한 관심이 높아지고 있다. 본 논문은 IEC-61850 표준규격을 분석하여 제시된, 거리 계전 IED 모델을 이용해 송전선 보호 IED를 구현하였다. 통신기능 구현은 리눅스 커널 2.6 기반의 통신보드를 사용하였고 계전 알고리즘의 수행은 TMS320C32 기반의 DSP(Digital Signal Processor) 보드를 사용하였다. 보드간 통신은 CAN(Cont roller Area Network) 통신으로 이루어 졌으며 사례연구를 위해 RTDS(Real Time Digital Power System Simulator)를 이용하여 입력신호를 생성하였다. 구성된 시스템의 검증을 위해 거리계전기에서 후비보호 시 발생할 수 있는 문제점을 시뮬레이션 하였다.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.647-655
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• 2008

This paper presents real-time algorithm for an ultrasonic Local Positioning System(LPS). An ultrasonic LPS consists of 4 transmitters and n receivers. Each transmitter transmits an sequential ultrasonic signal to avoid interference of ultrasonic signal. This method is a noneffective application for a fast object. Because receiver detects four sequential transmissive ultrasonic signal and calculates a position. This paper proposes the method which 4 transmitters transmit simultaneous ultrasonic signal and each transmitter distinguished by frequencies and codes. And Auto-Correlation Function(ACF) method separates codes from an ultrasonic echo signal which is interference of each transmitter's code. If the receiver uses only ACF method, it is difficult to implement real time application for increased computation. This paper implements LPS using dual frequencies and ACF method. Using dual frequencies reduces codes length. The reduced codes length save computation in ACF. To prove this algorithm by experiment, high performance DSP(digital signal processor) used. The result shows the performance of the designed system is good enough positioning.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.124-131
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• 1997

There have been many demands for th ereal-time image compression. The image compression systems have a wide range of applications. However, real-time encoding is hard to implement because it needs a large amount of computations. In particular, the discrete cosine transform (DCT) and motion estimatio require a large number of arithmetic oeprations compared to other algorithms in MPEG-2. The conventional fasdt DCT algorithms have focused on the reduction of the number of additions more cycles and more expense in realization. Because TMS320C80 has special structure, new approach for implementation of DCT is suggested. The selection of adaptive algorithm and optimization is requried TMS320C80 are analyzed an dsome adaptive DCT algorithms are selected. The DCT algorithms are optimized and implemented. Chens and lees DCT algorithms among various fast algorithms are selected because 1-D approach is effective in the view of th einternal structure of TMS320C80. According to the simulation result, Lees algorithm is more effective in speed and has little difference in precision. On the basis of the result, the possibility of DCT implementation for real-time MPEG-2 system is verified and the required number of the processor, called advanced DSP, is decided for real-time MPEG-2 encoding and decoding.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.142-146
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• 2012

Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.129-132
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• 2002

AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.