• Journal of Information Processing Systems
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• v.15 no.2
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• pp.374-385
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• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.61-68
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• 2005

A chip, which can fast encoder the audio data to AAC (Advanced Audio Coding) LC(Low Complexity) that is MPEG-2 audio standard, has been designed on the basis of a 32 bits DSP core and fabricated with 0.25um CMOS technology. At first, the various optimization methods for implementing the algerian are devised to reduce the memory size and calculation cycles. FFT(Fast Fourier Transform) hardware block is added to the DSP core to get the more reduction of the calculation cycles. The chips has the size of $7.20\times7.20 mm^2$ and about 830,000 equivalent gates, can carry out AAC encoding under 70MIPS(Million Instructions per Second).

• Proceedings of the Korea Contents Association Conference
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• 2008.05a
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• pp.116-120
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• 2008

Smart Camera provides intelligent vision functionalities which can interpret captured video, extract context-aware information and execute a necessary action in real-timeliness in addition to the functionality of network cameras which transmit the compressed acquired videos through networks. Intelligent vision algorithms demand tremendous computations so that real-time processing of computation of intelligent vision algorithms as well as compression and transmission of videos simultaneously is too much burden for a single CPU. Davinci processor of Texas Instruments is a popular ASSP(Application Specific Standard Product) which has dual core architecture of ARM core and DSP core and provides various I/O interfaces as well as networking interface and video acquiring interface necessary for developing digital video embedded applications. In this paper, we report the results of designing and implementing S/W for Davinci-based smart camera. We implement a face detection as an example of vision application and verify the implementation works well. In the future, for the development of a smart camera with more broad and real-time vision functionalities, it is necessary to study about more efficient vision application S/W architecture and optimization of vision algorithms on DSP core of Davichi processor.

• The Journal of the Acoustical Society of Korea
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• v.25 no.2
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• pp.61-71
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• 2006

An MP3 encoder chip has been designed and fabricated with the hardware and software co-design concepts. In the aspect of the software. the calculation cycles of the distortion control loop. which requires most of the calculation cycles in MP3 encoding procedure. have been reduced to $67\%$ of the original algorithm through the 'scale factor Pre-calculation'. By using a floating Point 32 bit DSP core and designing the FFT block with the hardware. we can get the additional reduction of the calculation cycles in addition to the software optimization. The designed chip has been verified using HW emulation and fabricated via 0.25um CMOS technology The fabricated chip has the size of $6.2{\time}6.2mm^2$ and operates normally on the test board in the qualitative and quantitative aspect.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.1
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• pp.37-47
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• 2008

Exploitation of address generation units which are typically provided in DSPs plays an important role in DSP code generation since that perform fast address computation in parallel to the central data path. Offset assignment is optimization of memory layout for program variables by taking advantage of the capabilities of address generation units, consists of memory layout generation and address pointer assignment steps. In this paper, we propose an effective address pointer assignment method to minimize the number of address calculation instructions in DSP code generation. The proposed approach reduces the time complexity of a conventional address pointer assignment algorithm with fixed memory layouts by using minimum cost-nodes breaking. In order to contract memory size and processing time, we employ a powerful pruning technique. Moreover our proposed approach improves the initial solution iteratively by changing the memory layout for each iteration because the memory layout affects the result of the address pointer assignment algorithm. We applied the proposed approach to about 3,000 sequences of the OffsetStone benchmarks to demonstrate the effectiveness of the our approach. Experimental results with benchmarks show an average improvement of 25.9% in the address codes over previous works.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.2
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• pp.128-136
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• 2002

In this paper, we developed an acoustic echo canceller in real-time using TeakLite DSP Core, which will be placed in the vocoder chip of a mobile handset. Considering the limited computational capacity given to the acoustic echo canceller in a vocoder chip, we employed a FIR-type adaptive filter using a conventional NLMS algorithm. To begin with, we designed and implemented an acoustic echo canceller with floating-point format C-source code, and then converted it into fixed-point format through integer simulation. Then we programmed and optimized it in the assembler level to make it run ill real-time. After optimization procedure, the implemented echo canceller has approximately 624 words of program memory and 811 words of data memory. With 8 KHz sampling rate and 256 filter taps in the echo canceller that corresponds to 32 msec of echo delay, it requires 14.12 MIPS of computational capacity. For coverage of 16 msec echo delay, i.e., 128 filter taps, 9 MIPS is requited.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.428-433
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• 2001

This paper presents the control algorithm for maximum efficiency drives of an induction motor system with the high dynamic performance. This system uses a simple model of the induction motor that includes equations of iron losses. The model, which only requires the parameters of induction motor, is referred to a field-oriented frame. The minimum point of the input power can be obtained at the steady state condition. The reference torque and flux currents for the vector control of induction motors are calculated by the optimal efficiency control algorithm. The drive system with the proposed efficiency optimization controller has been implemented by a 32 bit floating point TMS320C32 DSP chip. The results show the effectiveness of the control strategy proposed for the induction motor drive.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.431-434
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• 2002

This paper presents an implementation of direct torque control(DTC) of Reluctance Synchronous Motor(RSM) with an efficiency optimization using the 32bit DSP TMS320C31. The influence of iron loss can not neglected as high speed and precision torque control of RSM, so the optimal current ration between torque current and exiting current analytically derived to drive RSM at maximum efficiency For RSM, torque dynamics can be maintained even with controlling the flux level because the generated torque is direct]y proportional to the stator current. The experimental results for an RSM are presented to validate the applicability of the proposed method. The developed control system is shown high efficiency features with 1.0Kw RSM having 2.57 ratio of d/q reluctance.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.218-223
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• 2002

광 디스크 드라이브에서의 서보 제어시스템에는 광 픽업에서 발생된 레이저 빔을 디스크 기록면의 데이터 트랙에 정확히 위치시키기 위한 제어 계를 갖고 있다. 광 디스크의 고배속화에 따른 외란의 주파수 대역의 증가에 따라 더욱 더 높은 샘플링 주파수로 레이저 빔의 위치 제어를 필요로 하게 되고, 여러 가지 알고리즘의 증가로 인해 DSP의 연산 부담은 증가하게 된다. 본 논문에서는 서보 제어에 필요한 알고리즘의 최적화된 하드웨어/소프트웨어 시스템을 구현하고 이를 이용한 실험 결과를 제시한다.