• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.211-219
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• 2018

This paper designs a nonlinear PI-type controller for the robust control of a boost DC-DC converter using a particle swarm optimization (PSO) algorithm. Based on the common knowledge that the transient responses can be improved if the P and I gains increase when the transient error is big, a nonlinear PI-type control design method is developed. A design procedure to autotune the nonlinear P and I gains is given based on a PSO algorithm. The proposed nonlinear PI-type controller is implemented in real time on a Texas Instruments TMS320F28335 floating-point DSP. Simulation and experimental results are given to demonstrate the effectiveness and practicality of the proposed method.

• Journal of Advanced Navigation Technology
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• v.19 no.6
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• pp.544-551
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• 2015

In this paper, the design and implementation results of the optical flow estimator (OFE) for moving object detection (MOD) in advanced driver assistance system (ADAS). In the proposed design, Brox's algorithm with global optimization is considered, which shows the high performance in the vehicle environment. In addition, Cholesky factorization is applied to solve Euler-Lagrange equation in Brox's algorithm. Also, shift register bank is incorporated to reduce memory access rate. The proposed optical flow estimator was designed with Verilog-HDL, and FPGA board was used for the real-time verification. Implementation results show that the proposed optical flow estimator includes the logic slices of 40.4K, 155 DSP48s, and block memory of 11,290Kbits.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.4
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• pp.401-407
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• 2000

Modern microprocessors exploit instruction-level parallel processing to increase the performance. Especially VLIW processors supported by the parallelizing compiler are used more and more in specific applications such as high-end DSP and graphic processing. Bus-based VLIW architecture was proposed for these specific applications and it was designed to reduce the overhead of forwarding unit and the instruction width. In this paper, a optimizing scheduling compiler developed for the proposed bus-based VLIW processor is introduced. First, the method to model interconnections between buses and resource usage patterns is described. Then, on the basis of the modeling, machine-dependent optimization techniques such as bus-to-register promotion, copy coalescing and operand substitution were implemented. Optimization techniques for general-purpose VLIW microprocessors such as selective scheduling and enhanced pipelining scheduling(EPS) were also implemented. The experiment result shows about 20% performance gain for multimedia application benchmarks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.503-512
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• 2001

The general DSP algorithm, like orthogonal transform or filter processing, needs efficient hardware architecture to compute inner product. The typical MAC architecture has high cost of silicon. Because of this reason, the distributed arithmetic without multiplier is widely used for implementing inner product. This paper presents the optimization to reduce required hardware in distributed arithmetic by using extraction method of adder sharing component. The optimization process uses Boltzmann-machine which is one of the neural network. This proposed method can solve problem that is increasing complexity depending on depth of inner product and compose optimal summation-network with the minimum FA and FF in a few time. The designed DCT by using Proposed method is more efficient than a ROM-based distributed arithmetic.

• Journal of Electrical Engineering and Technology
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• v.11 no.3
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• pp.715-723
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• 2016

This paper proposes a design of optimal PI(D) controller for brushless DC (BLDC) motor speed control by the particle swarm optimization (PSO), one of the powerful metaheuristic optimization search techniques. The proposed control system is implemented on the TMS320F28335 DSP board interfacing to MATLAB/SIMULINK. With Back EMF detection, the proposed system is considered as a class of sensorless control. This scheme leads to the speed adjustment of the BLDC motor by PWM. In this work, the BLDC motor of 100 watt is conducted to investigate the control performance. As results, it was found that the speed response of BLDC motor can be regulated at the operating speed of 800 and 1200 rpm in both no load and full load conditions. Very satisfactory responses of the BLDC system can be successfully achieved by the proposed control structure and PSO-based design approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.85-95
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• 2000

FIR digital filter is one of important blocks in DSP application. For more effective operation, lots of architecture are proposed. In our paper, we proposed a high speed FIR filter with area efficiency. To fast operation, we used transposed form filter as basic architecute. And, we used dual path registers line to wupport variation of filter operation, and filter cascade is also considered. To reduce area, we adopted truncated Booth multiplier to our filter design. As a result, we showed that filter area is reduced when filter optimization using of dual path registers line and truncated multiplier with same constraints againt previous method.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.3
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• pp.37-44
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• 2000

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.17-29
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• 1999

This paper presents a high level synthesis method targeting low power consumption for data-dominated CMOS circuits (e.g., DSP). The high level synthesis is divided into three basic tasks: scheduling, resource and register allocation. For lower power scheduling, we increase the possibility of reusing an input operand of functional units. For a scheduled data flow graph, a compatibility graph for register and resource allocation is formed, and then a special weighted network is then constructed from the compatibility graph and the minimum cost flow algorithm is performed on the network to obtain the minimum power consumption data path assignment. The formulated problem is then solved optimally in polynomial time. This method reduces both the switching activity and the capacitance in synthesized data path. Experimental results show 15% power reduction in benchmark circuits.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1383-1388
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• 2015

Proportional integral derivative (PID) control is one of the conventional control strategies. Industrial PID control has many options, tools, and parameters for dealing with the wide spectrum of difficulties and opportunities in manufacturing plants. It has a simple control structure that is easy to understand and relatively easy to tune. Injection mold is warming up to the idea of cycling the tool surface temperature during the molding cycle rather than keeping it constant. This “heating and cooling” process has rapidly gained popularity abroad. However, it has discovered that raising the mold wall temperature above the resin’s glass-transition or crystalline melting temperature during the filling stage is followed by rapid cooling and improved product performance in applications from automotive to packaging to optics. In previous studies, optimization methods were mainly selected on the basis of the subjective experience. Appropriate techniques are necessary to optimize the cooling channels for the injection mold. In this study, a digital signal processor (DSP)-based PID control system is applied to injection molding machines. The main aim of this study is to optimize the control of the proposed structure, including a digital PID control method with a DSP chip in the injection molding machine.

• Journal of the Korean Institute of Intelligent Systems
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• v.21 no.4
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• pp.530-535
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• 2011

This paper deals with the precise temperature control of the heater used at a weaving thread or a drawn process. For precise temperature control, we suggest a design method that is auto-tuning IMC-PID controller using an optimization method uDEAS. For this method, we model the roll heater from the measurement data and we automatically tune the low pass filter value of IMC-PID controller that satisfies stability and conrol performance. Finally, we implement the designed controller using DSP kit.