• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.17-28
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• 2010

This paper presents a new automatic TFT-LCD image quality optimization system using DSP for the first time. Since conventional manual method depends on experiences of LCD module developers, it is highly labor-intensive and requires several correction steps providing large gamma correction error. The proposed system optimizes automatically gamma adjustment and power setting registers in mobile TFT-LCD driver IC to reduce gamma correction error, adjusting time, and flicker. It contains module-under-test (MUT, TFT-LCD module), PC installed with program, multimedia display tester for measuring luminance and flicker, and control board for interface between PC and TFT-LCD module. We have developed a new algorithm using 6-point programmable matching technique with reference gamma curve and applying automatic power setting sequence. Developed algorithm and program are generally applicable for most of the TFT-LCD modules. It is realized to calibrate gamma values of 1.8, 2.0, 2.2 and 3.0, and reduce flicker level. The control board is designed with DSP and FPGA, and it supports various interfaces such as RGB and CPU. Developed automatic image quality optimization system showed significantly reduced gamma adjusting time, reduced flicker, and much less average gamma error than conventional manual method. We believe that the proposed system is very useful to provide high-quality TFT-LCD and to improve developing process using optimized gamma-curve setting and automatic power setting.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.4
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• pp.227-235
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• 2011

This paper describes a PMSM control algorithm for realizing a low-cost motor drive system using a general purpose microcontroller. The proposed sensorless algorithm consists of the current observer and the sensorless scheme based on instantaneous reactive power. Also the control board system is not the high-cost DSP(digital signal processor) system but the general purpose microcontroller and it allows to reduce the unit cost of the motor system. However the clock frequency of the proposed microcontroller is one-fifths for the clock frequency of the DSP. In addition, the switching frequency must be selected as the lower frequency because of complex mathematic modeling of the sensorless algorithm. the low switching frequency augments the noise of the motor and might make accurate speed control impossible. Thus this paper proposes the optimization method to supplement the drawback of the general purpose microcontroller and the usefulness of the proposed method is verified through the experiment.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.79-85
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• 2018

This paper presents an implementation method of Long Term Evolution-Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a general-purpose multicore Digital Signal Processor (DSP), TMS320C6670. Although the DSP provides some useful coprocessors such as turbo decoder, fast Fourier transformer, Viterbi Coprocessor, Bit Rate Coprocessor etc., it is specific to the base station platform implementation not the mobile terminal platform implementation. This paper shows an implementation method of the LTE-A PDSCH decoder using programmable DSP cores as well as the coprocessors of Fast Fourier Transformer and turbo decoder. First, it uses the coprocessor supported by the TMS320C6670, which can be used for PDSCH implementation. Second, we propose a core programming method using DSP optimization method for block diagram of PDSCH that can not use coprocessor. Through the implementation, we have verified a real-time decoding feasibility for the LTE-A downlink physical channel using test vectors which have been generated from LTE-A Reference Measurement Channel (RMC) Waveform R.6.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.3
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• pp.323-329
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• 2009

This paper presents an automatic LCD gamma control system using gamma curve optimization. It controls automatically gamma adjustment registers in mobile LCD driver IC to reduce gamma correction error and adjusting time. The proposed gamma system contains Module-Under-Test (MUT, LCD module), PC installed with program, multimedia display tester for measuring luminance, and control board for interface between PC and LCD module. Proposed algorithm and program are applicable for most of the LCD modules. It is realized to calibrate gamma values of 1.8, 2.0, 2.2 and 3.0. The control board is designed with DSP and FPGA, and it supports various interfaces such as RGB and CPU. Developed automatic gamma control system showed significantly reduced gamma adjusting time of 240 sec. and much less average gamma error of 11% than 42h and 27% with conventional manual method. We believe that the proposed system is very useful to provide high-quality LCD and to improve production process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.7C
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• pp.962-970
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• 2004

This paper presents an efficient implementation of the 2.4 kbps EHSX(Enhanced Harmonic Stochastic Excitation) speech coder on a TMS320C6701$^{TM}$ floating-point digital signal processor. The EHSX speech codec is based on a harmonic and CELP(Code Excited Linear Prediction) modeling of the excitation signal respectively according to the frame characteristic such as a voiced speech and an unvoiced speech. In this paper, we represent the optimization methods to reduce the complexity for real-time implementation. The complexity in the filtering of a CELP algorithm that is the main part for the EHSX algorithm complexity can be reduced by converting program using floating-point variable to program using fixed-point variable. We also present the efficient optimization methods including the code allocation considering a DSP architecture and the low complexity algorithm of harmonic/pitch search in encoder part. Finally, we obtained the subjective quality of MOS 3.28 from speech quality test using the PESQ(perceptual evaluation of speech quality), ITU-T Recommendation P.862 and could get a goal of realtime operation of the EHSX codec.c.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.2
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• pp.41-52
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• 2011

It is important to reduce computational complexity of de-blocking filter for real-time implementation, because it accounts for a great part of total computational complexity of the decoder. Because there are a lot of conditional branches and memory accesses in a decoding loop, it is not easy to speed up the de-blocking filter. Therefore, this paper presents a new algorithm of de-blocking filter minimizing conditional branches and memory accesses. The proposed structure of de-blocking filter enables filter operation to parallelize by software pipelining. The proposed optimization method was implemented on a TMS320DM6467 EVM board and we achieved approximately 46% cycle reduction, compared with that of FFmpeg.

• Journal of Broadcast Engineering
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• v.13 no.4
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• pp.452-462
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• 2008

In this paper, we address issues associated with the real-time implementation of the MPEG-1/2 Layer-II (or MUSICAM) and MPEG-4 ER-BSAC decoders for Digital Multimedia Broadcasting (DMB) on TMS320C64x+ that is a fixed-point DSP processor with a clock speed of 330 MHz. To achieve the real-time requirement, they should be optimized in different steps as follows. First of all, a C-code level optimization is performed by sharing the memory, adjusting data types, and unrolling loops. Next, an algorithm level optimization is carried out such as the reconfiguration of bitstream reading, the modification of synthesis filtering, and the rearrangement of the window coefficients for synthesis filtering. In addition, the C-code of a synthesis filtering module of the MPEG-1/2 Layer-II decoder is rewritten by using the linear assembly programming technique. This is because the synthesis filtering module requires the most processing time among all processing modules of the decoder. In order to show how the real-time implementation works, we obtain the percentage of the processing time for decoding and calculate a RMS value between the decoded audio signals by the reference MPEG decoder and its DSP version implemented in this paper. As a result, it is shown that the percentages of the processing time for the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders occupy less than 3% and 11% of the DSP clock cycles, respectively, and the RMS values of the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders implemented in this paper all satisfy the criterion of -77.01 dB which is defined by the MPEG standards.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2008.11a
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• pp.251-253
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• 2008

최근 유럽에서 DVB-T HDTV 방송 표준이 정하지면서 오디오 포맷으로 HE-AAC가 채택되었다. HE-AAC는 압축효율은 높지만 연산량이 높아 낮은 성능의 DSP에서 수행하기에는 어려움이 있다. DVB-T에서는 5.1채널을 사용하고 있어 더욱더 많은 연산을 필요로 한다. 본 논문은 ISO/DEC 14496-3 MPEG4 HE(High Efficiency)-AAC의 Level4에 해당하는 Multichannel Decoder를 최적화하여 구현하고. 가장 많은 연산을 필요로 하는 Synthesis Filter Bank에 제안된 알고리즘을 적용하여 연산량을 줄였고 대부분의 연산부를 어셈블리로 코드 최적화를 하여 작은 성능의 DSP를 사용하여 실시간 Multichannel HE-AAC Audio Decoder의 구현이 가능하게 하였다. DVB-T 오디오 시스템에 필수로 필요한 Audio Description, Dynamic Range Control, Downmix 등을 함께 구현하여 실제 수신기에 사용이 가능하도록 하였다. DSP는 Samsung의 CalmRISC16 + MAC24 core 를 사용하였다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.197-200
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• 1999

MPEG-4 오디오 부호기의 일부인 HVXC(Harmonic and Vector excitation Coding) 부호기는 음성의 무성음 구간에서는 CELP 코덱, 유성음 구간에서는 MBE 코덱을 이용하여 부호화하는 구조로서, 많은 연산량을 필요로 하여 범용DSP를 이용한 실시간 구현의 장애요소로 작용한다. 본 논문에서는 TMS320C6701 DSP를 이용하여 많은 연산 시간을 요하는 함수들에 대한 C언어 및 어셈블리 레벨의 최적화를 수행하여 HVXC 함수들의 실행시간을 단축하고 이를 라이브러리화 하여 실시간 구현에 이용가능 하도록 하였다.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.53-56
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• 2004

본 논문은 HMM 기반 임베디드 음성인식 시스템 구현에 관한 몇 가지 주제들을 설명한다. 임베디드 환경은 한정된 자원을 가지고 있고 그러한 가운데 타당한 인식률과 향상된 인식 속도를 얻기 위해서 몇가지 방법들을 이 논문에서 설명한다. 구현 환경은 DSP6711 기반에서 이루어졌다. 가우시안 mixture 계산 루틴을 부동소수점 연산에서 고정소수점 연산 및 software pipelining을 적용하였다. 고정소수점 변환 전과 후 비슷한 인식률을 얻었고 고정소수점 변환과 software pipelining 적용 후 연산 속도의 향상을 얻었다.