• Journal of the Korea Society of Computer and Information
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• v.8 no.4
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• pp.75-80
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• 2003

In this paper, we designed add current scan system basically. Although NDT system using AC method in now days had problem with limit of detection rate and limit of device organization, in this paper, we made up these problem so that designed device smaller than system used, reduction of cost of system organization and precision of measuring crack. Also, AC leakage flux system had high accuracy about minute crack in the surface and advantage of designing system easily so that we designed system for concerning about crack of surface. Furthermore, it can be able to detect exact crack of reference in wide area by using DSP320C31 chip to reduce the time of measuring crack.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.5
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• pp.728-733
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• 2010

The conventional electro-mechanical circuit break and relay are widely used in large-sized DC power system. However, recently due to high reliability, remote controllability and small power dissipation of a RSSPC(Remote Solid State Power Controller), high-friendly DC power systems have increasingly adopted the RSSPC as a essential element. In this paper, we have conducted a mathematical modeling to analyze the performance of the proposed RSSPC system with the optimal signal range for $I^2t$. Based on the calculation, the RSSPC system has been implemented by DSP.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.27-33
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• 2001

This paper presents a digital instrument for a DSP based power quality analysis in three phase power system where current waveform is non-sinusoidal. it is based on stand alone type TMS320C31 DSP(digital signal processor)board and on a special high-speed data acquisition system. Power quality of low power motor drives are analyzed and processed by using a simple average power algorithm, and result of power analysis are displayed by LCD in the proposed system. This paper also goes on to discuss the performance of an instrument prototype, both in terms of accuracy and speed of measurement under the transient and steady state condition.

• The Journal of the Acoustical Society of Korea
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• v.23 no.2
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• pp.117-124
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• 2004

In this paper, we have been implemented the QPSK-based underwater transmission systems using DSP in order to transmit the underwater image data. We have adopted a BDPA (Block Data Parallel Architecture) to control multiple DSPs used in the transmitter and receiver in order to transmit the image data in real-time. We also have developed GUI software in order to drive and to debug the implemanted system in real-time. We have executed open sea tests in order to analyze the performance of the implemented system at East Sea near Kosung in Kangwon-Do. As a result of these experiments, it has been demonstrated that 10 kbps image data can be received without errors at 30m and 80m depth points, while the distance between the transmitter and the receiver is up to 20m.

• KIPS Transactions on Computer and Communication Systems
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• v.2 no.2
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• pp.59-66
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• 2013

In this paper, we proposed an optimal ILP algorithm on memory address code generation for DSP in embedded system. This paper using 0-1 ILP formulations DSP address generation units should minimize the memory variable data layout. We identify the possibility of the memory assignment of variable based on the constraints condition, and register the address code which a variable instructs in the program pointer. If the process sequence of the program is declared to the program pointer, then we apply the auto-in/decrement mode about the address code of the relevant variable. And we minimize the loads on the address registers to optimize the data layout of the variable. In this paper, in order to prove the effectiveness of the proposed algorithm, FICO Xpress-MP Modeling Tools were applied to the benchmark. The result that we apply a benchmark, an optimal memory layout of the proposed algorithm then the general declarative order memory on the address/modify register to reduce the number of loads, and reduced access to the address code. Therefor, we proved to reduce the execution time of programs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.4
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• pp.508-514
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• 2020

To implement the continuously evolving mobile communication standards such as Long Term Evolution (LTE) and 5G, the Software Defined Radio (SDR) concept provides great flexibility and efficiency. For many years, a high-end Digital Signal Processor (DSP) System on Chip (SoC) has been developed to support multicore and various hardware coprocessors. This paper introduces the implementation of the SDR platform hardware using TI's TCI663x chip. Using the platform, LTE transport channel is implemented by interworking multicore DSP with Bit rate Coprocessor (BCP) and Turbo Decoder Coprocessor (TCP) and the performance is evaluated according to various implementation options. In order to evaluate the performance of the implemented LTE transport channel, LTE base station system was constructed by combining FPGA main board for physical channels, SDR platform board, and RF & Antenna board.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.325-331
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• 2006

This paper suggests the design methodology of a robust controller based on disturbance rejection controller using DSP. In this paper, we discuss process to put the disturbance rejection controller into practice, and examine the performance of disturbance rejection controller by implementing it on DSP based hardware to evaluate usefulness of controller. As a result, the proposed robust controller can not only stabilize system against disturbance ,but it improve controlling performance. And also, it shows convenient to put into practical use of industrial sites due to its easy implementation on the hardware.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2882-2884
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• 2005

본 논문에서는 인터넷을 통한 멀티미디어 스트리밍 서비스 환경에서 다양한 표준으로 압축된 컨텐츠의 디코딩을 지원하기 위하여 general purpose DSP (Digital Signal Processor) 기반의 멀티미디어 서비스 플랫폼을 구현하였다. 다양한 표준 방식으로 압축된 멀티미디어 컨텐츠를 재생하기 위하여 Host 프로세서와 DSP 구조의 하드웨어를 설계하고, 멀티미디어 코덱을 DSP에 다운로드하는 소프트웨어적인 기법을 적용하였다. 설계한 플랫폼의 동작을 검증하기 위하여 리눅스 기반에서 DSP를 제어하는 네트워크 클라이언트 소프트웨어를 구현하고, Tl의 TMS 320C6416을 대상으로 구현한 MPEG-2 비디오와 AC-3 오디오 코덱을 적용하여 스트리밍 환경에서 멀티미디어 데이터가 원활하게 재생되는 것을 보였다.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.453-455
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• 1993

In this research, the digital signal processing PC board which employs TI's TMS320C25 is implemented. The board can perform following functions. spectrum analysis of speech and repetitive signal, digital filters emulation by convolution, signal generation of sinusoidal wave, rectangular wave etc.. In this system, communications between PC and DSP board. program down-loading to DSP board and recording and graphic of acquired and processed data in DSP board are executed by PC. Parallel interface and buffer memory are used in communications. Data acquisition and operation are carried out in DSP board. Resultant data are transmitted to PC and output through DAC.