• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.255-257
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• 2006

This paper proposed a platform which includes both Network processor and DSP for flexible IED. The Network processor is one of the Intel's IXP4XX Product Line family and the DSP is one of the TI's C6000 family. An embedded Linux is ported in Network processor so that a DSP program can be downloaded to Network processor through ethernet and then downloaded to DSP. Using this method, various algorithms according to IED can be applied to the Network processor board. Maximum ten ADCs can be connected because there is a CPLD between DSP and ADC. That is, the network processor board which can measure maximum 40 channels is implemented. In DSP program, thread and double buffering methods are used not to miss voltage samples. The Network processor board is verified using a method that eight channel voltage signals converted to digital are transmitted to server through both DSP and IXP425.

• MALSORI
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• no.52
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• pp.121-132
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• 2004

This paper is aiming at real-time implementation of adaptive noise cancellation system using DSP processor. ACHARF algorithm, which guarantees stability and fast convergence by adaptive compensator, is used on this DSP system. For the experiments, TLV320AIC23 stereo CODEC of TI Inc. is used with TMS320C6413 DSP processor. Signals of primary input and reference input are obtained by two microphones. The primary input is the voice plus noise signal and the reference input is white noise or real noise. The experimental results show that ANC system using DSP processor with ACHARF is verified to be an effective speech enhancement method for various speech processing units.

• ICROS
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• v.4 no.2
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• pp.15-17
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• 1998

DSP(Digital Signal Processor)는 신호처리의 응용에 있어서 실시간 처리가 요구되는 경우 탁월한 성능을 나타낸다. 멀티미디어 서비스를 위해서는 전송되어 들어오는 데이터를 빠른 시간에 처리를 하여 원하는 서비스를 제공해야 한다. 따라서 사용자 측에서는 전송된 데이터의 실시간 처리를 위한 특별한 장치가 요구된다. 본 논문에서는 이러한 용도를 위해 DSP를 이용하여 MSP(Multimedia Signal Processor)를 설계한다.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.3
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• pp.323-328
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• 2008

This paper presents a Digital Signal Processor achieving high through-put for both decision intensive and computation intensive tasks. The proposed processor employees a multiplier, two ALU and load/store. Unit as operational units. Those four units are controlled and works parallel by superscalar control scheme, which is different from prior DSP architecture. The performance evaluation was done by implementing AC-3 decoding algorithm and 37.8% improvement was achieved. This study is valuable especially for the consumer electronics applications, which require very low cost.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.2
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• pp.141-147
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• 2020

We studied for GPU based signal processor for naval multi-function radar. We implemented processing software both DSP and GPU, and compared computation performances and power consumption. As a result, computation performance was enhanced from 1.2 to 4.1 times compared with a DSP result. From the results, GPU can alternating DSP based signal processor for common radar processor even though Naval Multi Function Radar.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.5
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• pp.333-340
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• 2003

Doppler processing is the heart of pulsed Doppler radar. It gives a clutter elimination and coherent integration. With the improvement of digital signal processors (DPSs), the implementation using them is more widely used in radar systems. Generally, so as for Doppler processor to process the input data in real time, a parallel processing concept using multiple DSPs should be used. This paper implements a programmable Doppler processor, which consists of MTI filter, DFB and square-law detector, using 8 ADSP21060s. Formulating the distribution time of the input data, the transfer time of the output data and the time required to compute each algorithm, it estimates total processing time and the number of required DSP. Finally, using the TSG that provides radar control pulses and simulated target signals, performances of the implemented Doppler processor are evaluated.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.833-837
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• 2004

The iris image recognition system realization using DSP processor for the faster real-time processing is presented in this paper. The system is composed of CCD camera, DSP processing and network part to link the communication. The system based on high speed DSP processor leads the iris recognition processing time to be faster. The simulation results in 0.9sec below approximately.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.149-153
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• 2004

A Impulse denosing filter design of image for the faster processing time and system compatibility using DSP processor is presented on this paper The system hardware is composed of the stand-alone board with 32 bits DSP processor and vision board for image data acquisition with NTSC CCD camera, and the host computer controls them. The denoising method uses the adaptive median filter. The experiment result is that the system leads to denosing effect as 90% and PSNR 22㏈

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.264-267
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• 2003

The stereoscopic vision robot system design with DSP processor is presented. The vision system is consists of control system, vision system and host computer. The vision system is based on 32bits DSP processor. The stereoscopic image processing applies the correlation coefficient method to execute the software. The result of experiment, image recognition rate is 95% on the stereoscopic vision robot system.