• The KIPS Transactions:PartA
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• 제13A권5호
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• Journal of Sensor Science and Technology
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• 제20권3호
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• pp.172-177
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• 2011

Finger patients can't use their hands because of the paralysis their fingers. Their fingers are recovered by rehabilitating training, and the rehabilitating extent can be judged by measuring the pressing force to be contacted with two fingers(thumb and first finger, thumb and middle finger, thumb and ring finger, thumb and little finger). At present, most hospitals have used a thin plastic-plate for measuring the two-finger grasping force, and we can only judge that they can grasp the plate with their two-finger through it, because the plate can't measure the two-finger grasping force. But, recently, the force measuring system for measuring two-finger grasping force was developed using three-axis force sensor, but it is very expensive, because it has a three-axis force sensor. In this paper, two-finger force measuring system with a one-axis force sensor which can measure two-finger grasping force was developed. The one-axis force sensor was designed and fabricated, and the force measuring device was designed and manufactured using DSP(Digital Signal Processing). Also, the grasping force test of men was performed using the developed two-finger force measuring system, it was confirmed that the grasping forces of men were different according to grasping methods, and the system can be used for measuring two-finger grasping force.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제33권12A호
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• pp.1172-1176
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• 2008

In this paper, we describe the implementation and performance of a dual-mode Software Define Radio (SDR) smart antenna base station system. SDR technology enables a communication system to be reconfigured through software downloads to the flexible hardware platform that is implemented using programmable devices such as Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), and microprocessors. The presented base station channel card comprises the physical layer (pHY) including the baseband modem as well as the beamforming module. This channel card is designed to support TDD High-Speed Downlink Packet Access (HSDPA) as well as Wireless Broadband Portable Internet (WiBro) utilizing the SDR technology. We first describe the operations and functions required in WiBro and TDD HSDPA. Then, we explain the channel card design procedure and hardware implementation. Finally, we evaluate WiBro and TDD HSDPA performance by simulation and actual channel-card-based processing. Our smart antenna base-station dual-mode channel card shows flexibility and tremendous performance gains in terms of communication capacity and cell coverage.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제37권5호
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• pp.94-104
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• 2000

The accuracy and reliability of the target tracking is very critical issue in the design of automotive collision warning radar A significant problem in multi-target tracking (MTT) is the target-to-measurement data association If an incorrect measurement is associated with a target, the target could diverge the track and be prematurely terminated or cause other targets to also diverge the track. Most methods for target-to-measurement data association tend to coalesce neighboring targets Therefore, many algorithms have been developed to solve this data association problem. In this paper, a new multi-target data association method based on order statistics is described The new approaches. called the order statistics probabilistic data association (OSPDA) and the order statistics joint probabilistic data association (OSJPDA), are formulated using the association probabilities of the probabilistic data association (PDA) and the joint probabilistic data association (JPDA) filters, respectively Using the decision logic. an optimal or near optimal target-to-measurement data association is made A computer simulation of the proposed method in a heavy cluttered condition is given, including a comparison With the nearest-neighbor CNN). the PDA, and the JPDA filters, Simulation results show that the performances of the OSPDA filter and the OSJPDA filter are superior to those of the PDA filter and the JPDA filter in terms of tracking accuracy about 18% and 19%, respectively In addition, the proposed method is implemented using a developed digital signal processing (DSP) board which can be interfaced with the engine control unit (ECU) of car engine and with the d?xer through the controller area network (CAN)

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제17권8호
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• pp.773-787
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• 2006

An airborne radar is an essential aviation electronic system for the aircraft to perform various civil and/or military missions in all weather environments. This paper presents the design, development, and test results of the multi-mode X-band pulsed Doppler radar system test model for helicopter-borne flight test. This radar system consists of 4 LRUs(Line-Replacement Unit), which include antenna unit, transmitter and receiver unit, radar signal & data processing unit and display Unit. The developed core technologies include the planar array antenna, TWTA transmitter, coherent I/Q detector, digital pulse compression, MTI, DSP based Doppler FFT filter, adaptive CFAR, moving clutter compensation, platform motion stabilizer, and tracking capability. The design performance of the developed radar system is verified through various ground fixed and moving vehicle test as well as helicopter-borne field tests including MTD(Moving Target Detector) capability for the Doppler compensation due to the moving platform motion.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제21권8호
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• pp.857-864
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• 2010

In this paper, we analyse the effect of the path imbalances(gain and phase mismatches) in LINC(LInear amplification with Nonlinear Component) system, and propose a simple scheme using LUTs(Look Up Table) to compensate the path imbalances. The EVM(Error Vector Magnitude) and ACPR(Adjacent Channel Power Ratio) of the LINC system are degraded significantly by the path imbalances because it adopts an outphasing technique. The EVM and ACPR are theoretically extracted for two variables(gain and phase mismatch factors) and 2-D LUTs for those are generated based on the analysis. The efficient and simple compensation scheme for the path imbalances is proposed using the 2-D LUTs. A LINC system with the suggested compensation scheme is implemented, and the proposed method is verified with an experiment. A 16-QAM signal with 1.5 MHz bandwidth is used. Before the compensation, the path gain ratio was 95 % and phase error was $19.33^{\circ}$. The proposed scheme adjusts those values with 99 % and $0.5^{\circ}$, and improves ACPR about 18.1 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제40권6호
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• pp.447-458
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• 2003

A high speed multiplier is essential basic building block for digital signal processors today. Typically iterative algorithms in Signal processing applications are realized which need a large number of multiply, add and accumulate operations. This paper describes a macro block of a parallel structured multiplier which has adopted a 32$\times$32-b regularly structured tree (RST). To improve the speed of the tree part, modified partial product generation method has been devised at architecture level. This reduces the 4 levels of compression stage to 3 levels, and propagation delay in Wallace tree structure by utilizing 4-2 compressor as well. Furthermore, this enables tree part to be combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, combined with four modular block to construct a CSA tree (carry save adder tree). Therefore, multiplier architecture can be regularly laid out with same modules composed of Booth selectors, compressors and Modified Partial Product Generators (MPPG). At the circuit level new Booth selector with less transistors and encoder are proposed. The reduction in the number of transistors in Booth selector has a greater impact on the total transistor count. The transistor count of designed selector is 9 using PTL(Pass Transistor Logic). This reduces the transistor count by 50% as compared with that of the conventional one. The designed multiplier in 0.25${\mu}{\textrm}{m}$ technology, 2.5V, 1-poly and 5-metal CMOS process is simulated by Hspice and Epic. Delay is 4.2㎱ and average power consumes 1.81㎽/MHz. This result is far better than conventional multiplier with equal or better than the best one published.

• The KIPS Transactions:PartA
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• 제13A권4호
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.