• The KIPS Transactions:PartA
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• v.12A no.4 s.94
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• pp.305-312
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• 2005

In this paper, we present algorithm-level techniques for energy-efficient design at the algorithm level using FPGAs. We then use these techniques to create energy-efficient designs for two signal processing kernel applications: fast Fourier transform(FFT) and matrix multiplication. We evaluate the performance, in terms of both latency and energy efficiency, of FPGAs in performing these tasks. Using a Xilinx Virtex-II as the target FPGA, we compare the performance of our designs to those from the Xilinx library as well as to conventional algorithms run on the PowerPC core embedded in the Virtex-II Pro and the Texas Instruments TMS320C6415. Our evaluations are done both through estimation based on energy and latency equations on high-level and through low-level simulation. For FFT, our designs dissipated an average of $50\%$ less energy than the design from the Xilinx library and $56\%$ less than the DSP. Our designs showed an EAT factor of 10 times improvement over the embedded processor. These results provide a concrete evidence to substantiate the idea that FPGAs can outperform DSPs and embedded processors in signal processing. Further, they show that PFGAs can achieve this performance while still dissipating less energy than the other two types of devices.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.191-197
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• 2005

Biped walking is the main feature of a humanoid robot. In a biped walking robot, there are many actuators to be controlled and many sensors to be interfaced. In this paper, we propose a DSP-based controller for a miniature biped walking robot with 21 RC servo motors. The proposed controller has a hierarchical structure; a host PC, a DSP-based main controller, and an auxiliary controller with an FPGA chip. The host PC generates and transmits the robot walking data for given walking parameters such as stride, walking period, etc. The main controller implemented with a TMS320LF2407A controls 21 RC servo motors via the auxiliary controller. We also perform some experiments for balancing motion and walking on a slope terrain with interfacing a 2-axis acceleration sensor and a TMS320LF2407A.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

• KIPE Magazine
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• v.9 no.2
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• pp.26-30
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• 2004

전력전자 분야에서 사용되는 전동기 제어 시스템 또는 UPS, 능동필터 등 반도체 전력회로 제어에 다양한 신호처리와 고속연산이 가능하도록 하드웨어적으로 부동소숫점을 연산하거나 MAC 연산 기능 등이 있어 계산 속도가 빠르다는 장점 때문에 TMS320C3X등의 DSP가 많이 사용되어 왔다. 그런데 DSP는 입/출력 기능이 상당히 떨어지므로 외부에 A/D 변환기, EPLD 또는 FPGA 등의 외부소자 들이 많이 필요하여 회로가 상당히 복잡하다는 문제가 있었다. 이에 비하여 마이크로제어기는 입/출력 기능이 우수하나 연산속도가 상당히 떨어진다는 단점이 있다.(중략)

• The Journal of the Acoustical Society of Korea
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• v.30 no.3
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• pp.115-122
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• 2011

In this paper, we present a method to estimate an accurate real-time sound source direction based on time delay of arrival by using generalized cross correlation with four cross-type microphones. In general, existing systems have two disadvantages such as system embedding limitation due to the necessity of data acquisition for signal processing from microphone input, and real-time processing difficulty because of the increased number of channels for sound direction estimation using DSP processors. To cope with these disadvantages, the system considered in this paper proposes hardware design for enhanced real-time processing using microphone array signal processing. An accurate direction estimation and its design time reduction is achieved by means of an efficient hardware design using spatial segmentation methods and verification techniques. Finally we develop a system which can be used for embedded systems using a sound codec and an FPGA chip. According to experimental results, the system gives much faster real-time processing time compared with either PC-based systems or the case with DSP processors.

• The Magazine of the IEIE
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• v.23 no.11
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• pp.61-71
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• 1996

• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.2939-2941
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• 2000

FPGA는 ASIC설계의 시험을 위한 테스트용으로 많이 사용되었으나 최근에는 비약적인 성능 향상으로 그 자체로 기능을 구현하고 있다 퍼지 제어기의 구현은 일반적으로 범용 마이크로 프로세서를 이용하거나 DSP 프로세서를 이용하였다. 본 논문에서는 여러 퍼지 시스템 중에서 적은 규칙수로도 효과적인 성능을 나타내고 프로세서화가 용이한 TSK 퍼지 시스템을 구현한다. 대상 FPGA는 Xilinx사의 FPGA를 이용하고 Schematic과 VHDL을 혼용하여 설계한다 또한 구현된 프로세서의 범용성을 유지하기 위해 외부 ROM에서 연산에 필요한 계수를 취하는 방식을 채택 한다.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.251-254
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• 2000

본 논문은 IBAC(FM In Band Adjacent Channel) 방식의 디지털 오디오 방송(DAB; Digital Audio Broadcasting) 시스템 구현을 기술한 것이다. 구현한DAB 시스템은 현재 방송중인 FM방송의 인접 대역을 사용하기 위한 것으로, DAB 방송을 위해 주파수대역을 추가로 할당할 필요가 없으므로 주파수대역의 효율을 높일 수 있고 가용주파수 대역이 부족한 지역의 주파수할당에 대한 문제점을 해결할 수 있다.