• IEMEK Journal of Embedded Systems and Applications
• /
• v.12 no.3
• /
• pp.177-184
• /
• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.6
• /
• pp.124-130
• /
• 1989

For the higher density DRAM'S, innovations in fabrication process and circuit design which have led to dramatic density improvement are discussed from the desinger's perspective. A new dynamic RAM cell called Trench Epitaxial Transistor Cell(TETC) using trench technics and SEG have been developed for use in future megabit DRAMS. Storge electrode with $n^+$-polysilicon and $n^+$-source electrode are self-contacted in TETC. With keeping the storage capacitance large enough to prevent soft errors, the cell size reduced to 30% compare with existing BSE cell by utilizing the vertical capacitor made along the isolation region.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.12
• /
• pp.64-70
• /
• 1994

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.3
• /
• pp.173-179
• /
• 2002

We propose a novel sensing circuit for 2T-2MTJ MRAM that can be used for high speed synchronous operation. Proposed bit-line sense amplifier detects small voltage difference in bit-lines and develops it into rail-to-rail swing while maintaining small voltage difference on TMR cells. It is small enough to fit into each column that the whole data array on selected word line are activated as in DRAMs for high-speed read-out by changing column addresses only. We designed a 256Kb read-only MRAM in a $0.35\mu\textrm{m}$ logic technology to verify the new sensing scheme. Simulation result shows a 25ns RAS access time and a cycle time shorter than 10 ns.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.6
• /
• pp.901-909
• /
• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.6
• /
• pp.151-157
• /
• 1996

We propose a mechanism for the formation of pinholes in the Si-buffer layer, through the observations with varying the process- and structure variables in the SEPOX (selective poly-oxidation) process, an isolation method for sub-u DRAMs. Pinholes are formed through the accumulation of Si vacancies generated by the oxidation of Si, in which Si atoms leave the sites (vacancies) at the Si/SiO$_{2}$ interfaces and diffuse into the oxide to be oxidized near interface. In the course of the accumulation of Si-vacancies, the stress induced in the Si-buffer layer affects the migration of vacancies to result in the final size and distribution of pinholes. This paper may be, to our knowledge, the first report about the oxidation-induced pinhole in the Si/SiO$_{2}$ system.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.34D no.12
• /
• pp.62-67
• /
• 1997

The optical lithography wit an ArF excimer laser as a light source is expected to be used in the mass production of giga-bit DRAMs which require less than 0.2.mu.m minimum feature size. In this case, the distortion of a patterned image becomes very severe, since the lithography porcess is performed at the resolution limit. Traditionally, the photomask pattern was designed and revised with trial-and-error methods, such as repeated execution of process simulators or actual process experiments which require time and effort. Ths paper describes a program which automatically finds an optimal mask pattern. The program divides the mask plane into cells with same sizes, chooses a cell randomly, changes the transparent/opaque property of the cell, and eventually genrates a mask pattern which produces required image pattern. The program was applied to real DRAM cell patterns to produce mask patterns which genertes image patterns closer to object images than original mask patterns.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.4
• /
• pp.252-256
• /
• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.113-116
• /
• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• KIEE International Transactions on Electrophysics and Applications
• /
• v.11C no.2
• /
• pp.18-22
• /
• 2001

The thin films of high permitivity in ferroelectric materials using a capacitor are applied to DRAMs and FRAMs. (Ba, Sr)TiO$_3$ thin as ferroelectric materials were prepared by the sol-gel method and made by spin-coating on the Pt/Sio$_2$/Si substrate at 4,000 [rpm] for 10 seconds. The structural characteristics of the surface were analyzed by fractal dimension. The thickness of BST ceramics thin films was about 260∼280 [nm]. The property of the leakage current was stable with 10-9∼10-11[A] when the applied voltage was 0∼3[V]. BST thin films ha low leakage current properties when fractal dimension was low and a coating area was high.