• Electrical & Electronic Materials
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• v.13 no.12
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• pp.6-9
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• 2000

Over the years of decades, the memory technology has progressed a long, marble way. As we have evidenced from the Intel's 1Kb DRAM in 1970 to the Gigabit era of 2000's, the road further ahead towards the Terabit era will be unfolded. The technology once perceived inconceivable is in realization today, and similarly roadblocks as we know of today mayvecome trivial issues for tomorrow. For the inquiring mind, the question is how the "puzzle"of tomorrow's memory technology is pieced-in today. The process will take place both in evolutionary and revolutionary ways. Among these, note-worthy are the changes in DRAM architecture and the cell process technology. In this paper, some technical approaches will be discussed to bring these aspects into a general overview and a per-spective with possibilities for the new memory technology will be presented.presented.

• The Korean Journal of Ceramics
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• v.3 no.3
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• pp.213-217
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• 1997

In this paper, the imparct of X-ray and plasma process-induced-damages to La doped Lead Zirconate Titanate (PLZT, (Pb1-xLa)(Zr0.5Ti0.5)O3) capacitor characteristics have been investigated from the viewpoint of gigabit scale dynamic random access memory (DRAM) applications. Plamsa damage causes asymmetric degradation on hysteresis characteristics of PLZT films. On the other hand, X-ray damage results in a symmetrical reduction of charge storage densities (Qc's) for both polarities. As La concentration increases in the films, the radiation hardness of PLZT films on X-ray and plasma exposures is improved. It is observed that the damaged devices are fully recovered by thermal annealing under oxygen ambient.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.17-20
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• 2000

Over the years of decades, the memory technology has progressed a long, marble way. As we have evidenced from the Intel’s 1Kb DRAM in 1970 to the Gigabit era of 2000’s, the road further ahead towards the Terabit era will be unfolded. The technology once perceived inconceivable is in realization today, and similarly roadblocks as we know of today may become trivial issues for tomorrow. For the inquiring mind, the question is how the “puzzle” of tomorrow’s memory technology is pieced-in today. The process will take place both in evolutionary and revolutionary ways. Among these, note-worthy are the changes in DRAM architecture and the cell process technology. In this paper, some technical approaches will be discussed to bring these aspects into a general overview and a perspective with possibilities for the new memory technology will be presented.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.

• Electrical & Electronic Materials
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• v.9 no.4
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• pp.336-343
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• 1996

We have studied the preparation and the properties of $Ba_{1-x}$Sr$_{x}$TiO$_{3}$(BST) thin films by using the sol-gel method. Through the comparison of the effects of various solvents and additives in making solutions, we establish the production method of the stable solution which generates the high quality of BST film. We also set up the heat-treatment conditions for depositing the BST thin film through the TGA and XRD analyses. Through the comparison of the surface conditions of BST films deposited on Pt/Ta/SiO$_{2}$/Si and Pt/Ti/SiO$_{2}$/Si substrates, we find that Ta is more efficient diffusion barrier of Si than Ti so that Ta layer prevents the formation of hillocks. We fabricate the planar type capacitor and measure the dielectric properties of the BST thin film deposited on the Pt/Ta/SiO$_{2}$/Si substrate. Dielectric constant and dielectric loss tangent at 1V, 10kHz, and leakage current density at 3V of the BST thin film are 339, 0.052 and 13.3.mu.A/cm$^{2}$, respectively.ely.

• Journal of Internet of Things and Convergence
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• v.9 no.1
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• pp.71-76
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• 2023

Recently, in order to store and manage big data, research and development of a high-performance storage system capable of stably accessing large data have been actively conducted. In particular, storage systems in data centers and enterprise environments use large amounts of SSD (solid state disk) to manage large amounts of data. In general, SSD uses FTL(flash transfer layer) to hide the characteristics of NAND flash memory, which is a medium, and to efficiently manage data. However, FTL's algorithm has a limitation in using DRAM more to manage the location information of NAND where data is stored as the capacity of SSD increases. Therefore, this paper introduces FTL policies that apply virtual memory to reduce DRAM resources used in FTL. The virtual memory-based FTL policy proposed in this paper manages the map data by using LRU (least recently used) policy to load the mapping information of the recently used data into the DRAM space and store the previously used information in NAND. Finally, through experiments, performance and resource usage consumed during data write processing of virtual memory-based FTL and general FTL are measured and analyzed.

• Korean Journal of Optics and Photonics
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• v.6 no.3
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• pp.188-200
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• 1995

A design of unit magnification 2-mirror system with high resolution is presented. It is for soft X-ray(wavelength of 13 nm) projection imaging and suitable for preparation of high density semiconductor chip. In general, a holosymmetric system with unit magnification has the advantage that both coma and distortion are completely eliminated. In our holosymmetric 2-mirror system, spherical aberration is addtionally removed by using two identical paraboloidal mirror surfaces and field curvature aberration is also corrected by balancing Petzval sum and astigmatism which depends on the distance between two mirrors, so that the system is a aplanatic flat-field paraboloidal 2-mirror holosymmetric system. This 2-mirror system is small in size, and has a simple configuration with rotational symmetry about optical axis, and has also small central obscuration. Residual finite aberrations, spot diagrams, and diffraction-based MTF's are analyzed for the check of performances as soft X-ray lithography projection system. As a result, the image sizes for the resolutions of$0.25\mum$and $0.18\mum$are 4.0 mm, 2.5 mm respectively, and depths of focus for those are $2.5\mum$, $2.4\mum$respectively. This system should be useful in the fabrication of 256 Mega DRAM or 1 Giga DRAM. DRAM.

• Journal of Platform Technology
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• v.11 no.4
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• pp.50-61
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• 2023

The advancement of various big data technologies has had a tremendous impact on many industries. Diverse big data research studies have been conducted to process and analyze massive data quickly. Under these circumstances, new emerging technologies such as high-capacity persistent memory (PMEM) and Compute Express Link (CXL) have lately attracted significant attention. However, little investigation into a big data "search" platform has been made. Moreover, most big data software platforms have been still optimized for traditional DRAM-based computing systems. This paper first evaluates the basic performance of Intel Optane PMEM, and then investigates both indexing and searching performance of Elasticsearch, a widely-known enterprise big data search platform, on the PMEM-based computing system to explore its effectiveness and possibility. Extensive and comprehensive experiments shows that the proposed Optane PMEM-based Elasticsearch achieves indexing and searching performance improvement by an average of 1.45 times and 3.2 times respectively compared to DRAM-based system. Consequently, this paper demonstrates the high I/O, high-capacity, and nonvolatile PMEM-based computing systems are very promising for big data search platforms.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.149-153
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• 2020

This paper presents a new page placement policy for DRAM/NVRAM hybrid main memory in smartphones. Unlike previous studies on hybrid memory systems, this paper performs the placement of pages based on the offline analysis of memory access behaviors as smartphone's memory accesses are skewed to a certain address ranges, which is consistent regardless of smartphone applications, specially for write operations. Thus, we aim at reducing the write traffic to NVRAM by the offline analysis results. Experimental results show that the proposed policy reduces the write traffic to NVRAM by 61% on average without performance degradations.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.