• Journal of Digital Contents Society
• /
• v.18 no.5
• /
• pp.943-948
• /
• 2017

Currently, embedded systems designed for specific applications are used extensively in consumer electronics, smart phones, autonomous vehicles, robots, and plant control, etc. In addition, the importance of DRAM, which has a great influence on the performance of an embedded processor constituting an embedded system, has been increasing day by day, and research on DRAM has been actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of an embedded processor through simulation. In this paper, we developed an embedded processor simulator capable of interworking with a DRAM simulator. We also analyzed the influence of the DRAM model, which operates correctly on a cycle-by-cycle basis, on the performance of the embedded processor by using the MiBench embedded benchmark.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.11a
• /
• pp.163-166
• /
• 2004

모바일향 90nm DRAM을 개발하기 위하여 비대칭 채널 구조를 갖는 Recess Channel Array Transistor (RCAT)로 cell transistor를 구현하였다. DRAM cell transistor에서 junction leakage current 증가는 DRAM retention time 열화에 심각한 영향을 미치는 요인으로 알려져 있으며, DRAM의 minimum feature size가 점점 감소함에 따라 short channel effect의 영향으로 junction leakage current는 더욱 더 증가하게 된다. 본 실험에서는 short channel effect의 영향에 의한 junction leakage current를 감소시키기 위하여 Recess Channel Array Transistor를 도입하였고, cell transistor의 채널 영역을 비대칭으로 형성하여 data retention time을 증가시켰다. 비대칭 채널 구조을 이용하여 Recess Channel Array Transistor를 구현한 결과, sub-threshold 특성과 문턱전압, Body effect, 그리고, GIDL 특성에는 큰 유의차가 보이지 않았고, I-V특성인 드레인 포화전류(IDS)는 대칭 채널 구조인 transistor 대비 24.8% 정도 증가하였다. 그리고, data retention time은 2배 정도 증가하였다. 본 실험에서 얻은 결과는 향후 저전압 DRAM 개발과 응용에 상당한 기여를 할 것으로 기대된다.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.2
• /
• pp.179-185
• /
• 2020

DRAM is a major component of the main memory system. As the operating system evolves and application complexity and capacity increases, the capacity and speed of DRAM are also increasing. DRAM should perform a refresh action of periodically reading and then re-storing stored values, and the accompanying performance and power/energy overhead embodies characteristics that worsen as capacity increases. This study proposes an energy efficiency improvement technique that efficiently stores the rows that need to be refreshed within 64ms and 128ms using the bloom filter for cells with the lowest retention time of electrons. The results of the experiment showed that the proposed technique resulted in an average 5.5% performance improvement, 76.4% reduction in average refresh energy, and 10.3% reduction in average EDP.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.793-798
• /
• 2016

In this work, the memory window characteristics of vertical nanowire device with asymmetric source and drain was analyzed using bipolar junction transistor mode for 1T-DRAM application. A gate-all-around (GAA) MOSFET with higher doping concentration in the drain region than in the source region was used. The shape of GAA MOSFET was a tapered vertical structure that the source area is larger than the drain area. From hysteresis curves using bipolar junction mode, the memory windows were 1.08V in the forward mode and 0.16V in the reverse mode, respectively. We observed that the latch-up point was larger in the forward mode than in the reverse mode by 0.34V. To confirm the measurement results, the device simulation has been performed and the simulation results were consistent in the measurement ones. We knew that the device structure with higher doping concentration in the drain region was desirable for the 1T-DRAM using bipolar junction mode.

• 전기의세계
• /
• v.38 no.4
• /
• pp.20-23
• /
• 1989

memory설계는 고속, 저 전력, 고밀도, 응용다야화를 목표로 하고 있다. 세가지 목표는 기술적인 측면에서 해결해야 하며, 마지막 목표는 영업과 기술이 동시에 참여해야 달성할 수 있다. 이외에도 타사의 특허를 벗어나는 설계가 우리의 과제이기도 하다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2014.11a
• /
• pp.70-72
• /
• 2014

플래시 메모리는 소형 저장 장치뿐만 아니라 대용량 저장장치까지 응용되고 있다. 하지만 기존의 하드디스크 (HDD)와 다르게 플래시 메모리는 읽기, 쓰기, 소거 연산의 속도가 다르고 쓰기 전 지우기(erase before write)라는 특성 때문에 FTL의 한 메커니즘인 GC (Garbage Collection)를 수행할 때 많은 오버헤드가 발생한다. 이에 이 논문은 DRAM의 공간을 효율적으로 활용하고 유효한 페이지 복사와 소거 연산의 횟수를 줄여 전체적인 플래시 메모리 GC 오버헤드를 줄이기 위한 블록 링크드 리스트 기법을 제안한다. 블록 링크드 리스트 기법은 같은 LBN에 해당하는 데이터를 로그 블록에 적고 해당 로그 블록들을 링크드 리스트로 관리해 소거 연산을 미룰 수 있다. 링크드 리스트들에 관한 정보는 DRAM에 테이블 형태로 적는다. 이때 테이블에는 블록 주소들이 적히므로 페이지 단위로 링크드 리스트를 관리하는 다른 기법에 비해 DRAM의 공간을 효율적으로 활용하게 된다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.37 no.1
• /
• pp.19-26
• /
• 2010

In this paper, we adopt Storage Class Memory, which is next-generation non-volatile RAM technology, as part of main memory parallel to DRAM, and exploit the SCM+DRAM main memory system from the dependability perspective. Our system provides instant system on/off without bootstrapping, dynamic selection of process persistence or non-persistence, and fast recovery from power and/or software failure. The advantages of our system are that it does not cause the problems of checkpointing, i.e., heavy overhead and recovery delay. Furthermore, as the system enables full application transparency, our system is easily applicable to real-world environments. As proof of the concept, we implemented a system based on a commodity Linux kernel 2.6.21 operating system. We verify that the persistence enabled processes continue to execute instantly at system off-on without any state and/or data loss. Therefore, we conclude that our system can improve availability and reliability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.2
• /
• pp.133-137
• /
• 1998

$(Pb_{0.72}La_{0.28})Ti_{0.93}O_3(PLT(28))$ thin films were fabricated by pulsed laser deposition. PLT films deposited on $Pt/Ti/SiO_2/Si$ at $600^{\circ}C$ had a preferred orientation in (111) plane and at $550^{\circ}C$ had a (100) preferred orientation. We found that (111) preferred oriented films had well grown normal to substrate surface. This PLT(28) thin films of $1{\mu}m$ thickness had dielectric properties of ${\varepsilon}_r$=1300, dielectric $loss{\fallingdotseq}0.03 $. and had charge storage density of 10 [${\mu}C/cm^2$] and leakage current density of less than $10^{-6}[A/cm^2]$ at 100[kV/cm]. These results indicated that the PLT(28) thin films fabricated by pulsed laser deposition are suitable for DRAM capacitor application.

• The Journal of Korean Institute of Next Generation Computing
• /
• v.13 no.4
• /
• pp.40-51
• /
• 2017

Recently, as mobile workloads are becoming more data-intensive, high data bandwidth is required for mobile memory which also consumes non-negligible system energy. A variety of researches and technologies are under development to improve and optimize mobile memory technologies. However, a comprehensive study on the latest mobile memory technologies (LPDDR or Wide I/O) has not been extensively performed yet. To construct high-performance and energy-efficient mobile memory systems, quantitative and detailed analysis of these technologies is crucial. In this paper, we simulate the computer system which adopts mobile DRAM technologies (Wide I/O and LPDDR3). Based on our detailed and comprehensive results, we analyze important factors that affect performance and energy-efficiency of mobile DRAM technologies and show which part can be improved to construct better systems.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.291-294
• /
• 1998

The objective of this study is to deposited the preparation of STO dielectric thin films on Ag/barrier-mater/Si(N-type 100) bottom electrode using a conventional rf-magnetron sputtering technique with a ceramic target under various conditions. It is demonstrated that the leakage current of films are strongly dependent on the atmosphere during deposition and the substrate temperature. The resistivity properties of films deposited on silicon substrates were very high resistivity. Capacitance of the films properties were the highest value(1000pF) and dependent on substrate temperature.