• 전자공학회논문지 IE
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• v.47 no.4
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• pp.39-47
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• 2010

This paper proposes a numerical analysis to prove that the performance of the differential phase detections (DPDs) with the decision feedback, such as the decision feedback DPD (DF-DPD) and the DPD with recursively generated phase reference (DPD-RGPR), approach the performance of the coherent detection with differential decoding. The conventional differential phase detection for M-ary DPSK can make the receiver architecture simple, while it can make the bit-error rate (BER) performance poor because of the previous noisy phase as a reference phase. To improve the BER performance of the conventional differential detection, multiple symbol differential detection methods, including DF-DPD and DPD-RGPR, have been proposed. However, the studies on the analysis and on the comparison of these methods have been little performed. Then, this paper mathematically intends to analyze and compare the performance of the DPDs with the decision feedback. The analysis results show that the DPDs with the decision feedback can have the performance equal to that of the coherent detection with differential decoding and be available for the noncoherent detection in the improved performance. Considering the hardware complexity, the DPD RGPR with the simple detection process by using the recursively generated phase reference can be more simply implemented than the DF-DPD based on the architecture whose complexity increases according to the increasing detection length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.74-86
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• 2002

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.